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FIN3385 Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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FIN3385 Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 21 page © 2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN3385 / FIN3386 • Rev. 1.0.6 3 Transmitter Pin Configuration Figure 3. FIN3385 (28:4 Transmitter) Pin Assignments Pin Definitions Pin Names I/O Types Number of Pins Description of Signals TxIn I 28/21 LVTTL Level Input TxCLKIn I 1 LVTTL Level Clock Input, the rising edge is for data strobe TxOut+ O 4/3 Positive LVDS Differential Data Output TxOut- O 4/3 Negative LVDS Differential Data Output TxCLKOut+ O 1 Positive LVDS Differential Clock Output TxCLKOut- O 1 Negative LVDS Differential Clock Output R_FB I 1 Rising Edge Data Strobe: Assert HIGH (VCC) Falling Edge Data Strobe: Assert LOW (Ground) /PwrDn I 1 LVTTL Level Power-Down Input Assertion (LOW) puts the outputs in High-Impedance state PLL VCC I 1 Power Supply Pin for PLL PLL GND I 2 Ground Pins for PLL LVDS VCC I 1 Power Supply Pin for LVDS Output LVDS GND I 3 Ground Pins for LVDS Output VCC I 3 Power Supply Pins for LVTTL Input GND I 5 Ground Pin for LVTTL Input |
Similar Part No. - FIN3385_12 |
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Similar Description - FIN3385_12 |
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