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PPXN2020VMG116R Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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PPXN2020VMG116R Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
10 / 23 page PXN20 Product Brief, Rev. 1 Features Freescale Semiconductor 10 • Two RAM blocks implemented on separate crossbar ports to reduce arbitration events for high access master to on-chip RAM. — One port with 80 KB (PXN20 only) — One port with 512/128 KB RAM • Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if back to back with a read to same memory block • 32-bit ECC with single-bit correction, double bit detection for data integrity • Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory • User transparent ECC encoding and decoding for byte, half word, and word accesses 2.6.5 On-Chip Voltage Regulator (VREG) The on-chip voltage regulator includes the following features: • Single supply device • 3.3 V / 5 V (nominal) input supply voltage supported • Supports I/O levels independent of main supply — MLB has separate supply pins to support down to 2.5 V (nominal) operation — Multiple I/O domains with separate supply pins • Low voltage detectors (LVD) supported on internal supplies • Cold crank operation supported without triggering LVDs 2.6.6 Fast Ethernet Controller (FEC) The FEC incorporates the following features • Support for 3 different physical interfaces — 100 Mbps IEEE 802.3 MII — 10 Mbps IEEE 802.3 MII — 10 Mbps 7-wire interface (industry standard) • Built in FIFO and DMA controller • IEEE 802.3 MAC (compliant with IEEE 802.3 1998 edition) • Programmable max frame length supports IEEE 802.1 VLAN tags and priority • IEEE 802.3 full duplex flow control • Support for full duplex operation (200 Mbps throughput) with a system clock of 100 MHz using the external TX_CLK or RX_CLK • Support for full duplex operation(100 Mbps throughput) with a system clock of 50 MHz using the external TX_CLK or RX_CLK • Retransmission from transmit FIFO following a collision (no system bus utilization) • Automatic internal flushing of the receive FIFO for runts (collision fragments) and address recognition rejects (no system bus utilization) |
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