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PPXN3010VMS1R Datasheet(PDF) 1 Page - Freescale Semiconductor, Inc |
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PPXN3010VMS1R Datasheet(HTML) 1 Page - Freescale Semiconductor, Inc |
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1 / 139 page  Freescale Semiconductor Data Sheet: Advance Information Document Number: PXS30 Rev. 1, 09/2011 © Freescale Semiconductor, Inc., 2011. All rights reserved. Preliminary—Subject to Change Without Notice This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. PXS30 257 MAPBGA (14 x 14 mm) 473 MAPBGA (19 x 19 mm) The PXS30 family represents a new generation of 32-bit microcontrollers based on the Power Architecture®. These devices provide a cost-effective, single chip display solution for the industrial market. An integrated TFT driver with digital video input ability from an external video source, significant on-chip memory, and low power design methodologies provide flexibility and reliability in meeting display demands in rugged environments. The advanced processor core offers high performance processing optimized for low power consumption, operating at speeds as high as 64 MHz. The family itself is fully scalable from 512 KB to 1 MB internal flash memory. The memory capacity can be further expanded via the on-chip QuadSPI serial flash controller module. The PXS30 family platform has a single level of memory hierarchy supporting on-chip SRAM and flash memories. The 1 MB flash version features 160 KB of on-chip graphics SRAM to buffer cost effective color TFT displays driven via the on-chip Display Control Unit (DCU). See Table 1 for specific memory size and feature sets of the product family members. The PXS30 family benefits from the extensive development infrastructure for Power Architecture devices, which is already well established. This includes full support from available software drivers, operating systems, and configuration code PXS30 Microcontroller Data Sheet 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 Feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . 19 2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 70 3.3 Recommended operating conditions . . . . . . . . . . . . . . 71 3.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 73 3.5 Electromagnetic interference (EMI) characteristics . . . 74 3.6 Electrostatic discharge (ESD) characteristics. . . . . . . . 75 3.7 Static latch-up (LU). . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.8 Power Management Controller (PMC) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.9 Supply current characteristics . . . . . . . . . . . . . . . . . . . 78 3.10 Temperature sensor electrical characteristics . . . . . . . 78 3.11 Main oscillator electrical characteristics . . . . . . . . . . . . 79 3.12 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 79 3.13 16 MHz RC oscillator electrical characteristics . . . . . . 81 3.14 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . 81 3.15 Flash memory electrical characteristics . . . . . . . . . . . . 87 3.16 SRAM memory electrical characteristics . . . . . . . . . . . 89 3.17 GP pads specifications . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.18 PDI pads specifications . . . . . . . . . . . . . . . . . . . . . . . . 91 3.19 DRAM pad specifications . . . . . . . . . . . . . . . . . . . . . . . 96 3.20 RESET characteristics . . . . . . . . . . . . . . . . . . . . . . . . 102 3.21 Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.22 Peripheral timing characteristics. . . . . . . . . . . . . . . . . 110 4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.1 Package mechanical data. . . . . . . . . . . . . . . . . . . . . . 132 5 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 7 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 138 |
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