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SPXS3010VMS1R Datasheet(PDF) 9 Page - Freescale Semiconductor, Inc |
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SPXS3010VMS1R Datasheet(HTML) 9 Page - Freescale Semiconductor, Inc |
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9 / 139 page  Introduction PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 9 1.5.6 Frequency-Modulated Phase-Locked Loop (FMPLL) Two FMPLLs are available on each device. Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor and output clock divider ratio are software configurable. The FMPLLs have the following major features: • Input frequency: 4–40 MHz continuous range (limited by the crystal oscillator) • Voltage controlled oscillator (VCO) range: 256–512 MHz • Frequency modulation via software control to reduce and control emission peaks — Modulation depth ±2% if centered or 0% to –4% if downshifted via software control register — Modulation frequency: triangular modulation with 25 kHz nominal rate • Option to switch modulation on and off via software interface • Reduced frequency divider (RFD) for reduced frequency operation without re-lock • 2 modes of operation — Normal PLL mode with crystal reference (default) — Normal PLL mode with external reference • Lock monitor circuitry with lock status • Loss-of-lock detection for reference and feedback clocks • Self-clocked mode (SCM) operation • Auxiliary FMPLL — Used for FlexRay due to precise symbol rate requirement by the protocol — Used for motor control periphery and connected IP (A/D digital interface CTU) to allow independent frequencies of operation for PWM and timers as well as jitter-free control — Option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in electric motor control loop — Allows running motor control periphery at different (precisely lower, equal, or higher ,as required) frequency than the system to ensure higher resolution 1.5.7 External Bus Interface (EBI) • Available on 473-pin devices • Data and address options: — 16-bit data and address (non-muxed) — 32-bit data and address (bus-muxed) • MPC5561 324 BGA compatibility mode: 16-bit data bus, 24-bit address bus is default ADDR[8:31], but configurable to 26-bit address bus. • Memory controller with support for various memory types — Non-burst and burst mode SDR flash and SRAM — Asynchronous/legacy flash and SRAM |
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