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FAN2108 Datasheet(PDF) 10 Page - Fairchild Semiconductor |
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FAN2108 Datasheet(HTML) 10 Page - Fairchild Semiconductor |
10 / 14 page © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN2108 • Rev. 1.0.2 10 Circuit Description Initialization Once VCC exceeds the UVLO threshold and EN is HIGH, the IC checks for an open or shorted FB pin before releasing the internal soft-start ramp (SS). If R1 is open (Figure 1), the error amplifier output (COMP) is forced LOW and no pulses are generated. After the SS ramp times out (T1.0), an under-voltage latched fault occurs. If the parallel combination of R1 and RBIAS is ≤ 1 KΩ, the internal SS ramp is not released and the regulator does not start. Bias Supply The FAN2108 requires a 5 V supply rail to bias the IC and provide gate-drive energy. Connect a ≥ 1.0 µf X5R or X7R decoupling capacitor between VCC and PGND. Since VCC is used to drive the internal MOSFET gates, supply current is frequency and voltage dependent. Approximate VCC current (ICC) is calculated by: )] 128 ( ) 013 . 0 227 5 [( 58 . 4 ) ( − • + − + = f V I CC mA CC (1) where frequency (f) is expressed in KHz. Enable FAN2108 has an internal pull-up to enable pin so that the IC is enabled once VCC is applied. Connecting a small capacitor across EN and AGND delays the rate of voltage rise on the EN pin. EN pin also serves for the restart whenever a fault occurs (refer to the Auto-Restart section) . For applications where sequencing is required, FAN2108 can be enabled (after the VCC comes up) with external control, as shown in Figure 20. Figure 20. Enabling with External Control Setting the Frequency Oscillator frequency is determined by an external resistor, RT, connected between the R(T) pin and AGND. Resistance is calculated by: 65 135 ) / 10 ( 6 ) ( − = Ω f R K T (2) where RT is in K Ω and frequency (f) is in KHz. The regulator cannot start if RT is left open. Soft-Start Once internal SS ramp has charged to 0.8 V (T0.8), the output voltage is in regulation. Until SS ramp reaches 1.0 V (T1.0), the fault latch is inhibited. To avoid skipping the soft-start cycle, it is necessary to apply VIN before VCC reaches its UVLO threshold. Soft-start time is a function of oscillator frequency. SS 1.35V FB EN 0.8V T0.8 T1.0 3200 CLKs 4000 CLKs Fault Latch Enable 0.8V 1.0V 2400 CLKs Figure 21. Soft-Start Timing Diagram The regulator does not allow the low-side MOSFET to operate in full synchronous rectification mode until internal SS ramp reaches 95% of VREF (~0.76 V). This helps the regulator to start on a pre-biased output and ensures that inductor current does not "ratchet" up during the soft-start cycle. VCC UVLO or toggling the EN pin discharges the SS and resets the IC. Setting the Output Voltage The output voltage of the regulator can be set from 0.8 V to 80% of VIN by an external resistor divider (R1 and RBIAS in Figure 1). The internal reference is 0.8 V with 650 nA, sourced from the FB pin to ensure that, if the pin is open, the regulator does not start. The external resistor divider is calculated using: nA R V V R V OUT BIAS 650 1 8 . 0 8 . 0 + − = (3) Connect RBIAS between FB and AGND. |
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Similar Description - FAN2108_12 |
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