© 2006 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FSQ0170RNA, FSQ0270RNA Rev. 1.0.5

3

Pin Configuration

Figure 3. Pin Configuration (Top View)

Pin Definitions

Pin #

Name

Description

1GND

Ground. SenseFET source terminal on primary side and internal control

ground.

Power Supply. Positive supply voltage input. Although connected to an aux-

threshold (12V) that the internal start-up switch opens and device power is

supplied via the auxiliary transformer winding.

3FB

Feedback. The feedback voltage pin is the non-inverting input to the PWM

comparator. It has a 0.9mA current source connected internally while a capac-

itor and opto-coupler are typically connected externally. A feedback voltage of

6V triggers overload protection (OLP). There is a time delay while charging ex-

time delay prevents false triggering under transient conditions, but still allows

the protection mechanism to operate under true overload conditions.

Peak Current Limit. This pin adjusts the peak current limit of the SenseFET.

The 0.9mA feedback current source is diverted to the parallel combination of

an internal 2.8k

 resistor and any external resistor to GND on this pin. This

typical peak current limit is 0.8A (FSQ0170RNA), 0.9A (FSQ0270RNA).

Start-up. This pin connects to the rectified AC line voltage source. At start-up,

the internal switch supplies internal bias and charges an external storage ca-

the internal switch is opened.

6Drain

SenseFET drain. High-voltage power SenseFET drain connection.

7Drain

SenseFET drain. High-voltage power SenseFET drain connection.

8Drain

SenseFET drain. High-voltage power SenseFET drain connection.

GND

V

CC

I

PK

V

str

8-DIP

FB

D

D

D

FSQ0x70RNA Rev. 1.00