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W77C32 Datasheet(PDF) 5 Page - Winbond |
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W77C32 Datasheet(HTML) 5 Page - Winbond |
5 / 71 page Preliminary W77C32 Publication Release Date: March 1999 - 5 - Revision A1 W77C32 to work efficiently with both fast and slow RAMs and peripheral devices. In addition, the W77C32 contains on-chip 1KB MOVX SRAM, the address of which is between 0000H and 03FFH. It only can be accessed by MOVX instruction; this on-chip SRAM is optional under software control. The W77C32 is an 8052 compatible device that gives the user the features of the original 8052 device, but with improved speed and power consumption characteristics. It has the same instruction set as the 8051 family, with one addition: DEC DPTR (op-code A5H, the DPTR is decreased by 1). While the original 8051 family was designed to operate at 12 clock periods per machine cycle, the W77C32 operates at a much reduced clock rate of only 4 clock periods per machine cycle. This naturally speeds up the execution of instructions. Consequently, the W77C32 can run at a higher speed as compared to the original 8052, even if the same crystal is used. Since the W77C32 is a fully static CMOS design, it can also be operated at a lower crystal clock, giving the same throughput in terms of instruction execution, yet reducing the power consumption. The 4 clocks per machine cycle feature in the W77C32 is responsible for a three-fold increase in execution speed. The W77C32 has all the standard features of the 8052, and has a few extra peripherals and features as well. I/O Ports The W77C32 has four 8-bit ports and one extra 4-bit port. Port 0 can be used as an Address/Data bus when external program is running or external memory/device is accessed by MOVC or MOVX instruction. In these cases, it has strong pull-ups and pull-downs, and does not need any external pull- ups. Otherwise it can be used as a general I/O port with open-drain circuit. Port 2 is used chiefly as the upper 8-bits of the Address bus when port 0 is used as an address/data bus. It also has strong pull-ups and pull-downs when it serves as an address bus. Port 1 and 3 act as I/O ports with alternate functions. Port 4 is only available on 44-pin PLCC/QFP package type. It serves as a general purpose I/O port as Port 1 and Port 3. The P4.0 has an alternate function WAIT which is the wait state control signal. When wait state control signal is enabled, P4.0 is input only. Serial I/O The W77C32 has two enhanced serial ports that are functionally similar to the serial port of the original 8052 family. However the serial ports on the W77C32 can operate in different modes in order to obtain timing similarity as well. Note that the serial port 0 can use Timer 1 or 2 as baud rate generator, but the serial port 1 can only use Timer 1 as baud rate generator. The serial ports have the enhanced features of Automatic Address recognition and Frame Error detection. Timers The W77C32 has three 16-bit timers that are functionally similar to the timers of the 8052 family. When used as timers, they can be set to run at either 4 clocks or 12 clocks per count, thus providing the user with the option of operating in a mode that emulates the timing of the original 8052. The W77C32 has an additional feature, the watchdog timer. This timer is used as a System Monitor or as a very long time period timer. Interrupts The Interrupt structure in the W77C32 is slightly different from that of the standard 8052. Due to the presence of additional features and peripherals, the number of interrupt sources and vectors has been increased. The W77C32 provides 12 interrupt resources with two priority level, including six external interrupt sources, timer interrupts, serial I/O interrupts and power-fail interrupt. |
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