Preliminary W78E52B

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Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6

(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next

instruction cycle. The Watchdog timer is cleared on reset.

OSC

1/12

PRESCALER

14-BIT TIMER

CLEAR

CLRW

EXTERNAL

RESET

INTERNAL

RESET

WIDL

IDLE

ENW

Watchdog Timer Block Diagram

Typical Watch-Dog time-out period when OSC = 20 MHz

PS2 PS1 PS0

WATCHDOG TIME-OUT PERIOD

0

0

0

19.66 mS

0

1

0

39.32 mS

0

0

1

78.64 mS

0

1

1

157.28 mS

1

0

0

314.57 mS

1

0

1

629.14 mS

1

1

0

1.25 S

1

1

1

2.50 S

Clock

The W78E52B is designed to be used with either a crystal oscillator or an external clock. Internally,

the clock is divided by two before it is used. This makes the W78E52B relatively insensitive to duty

cycle variations in the clock. The W78E52B incorporates a built-in crystal oscillator. To make the

oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load

capacitor must be connected from each pin to ground. An external clock source should be connected

to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as

required by the crystal oscillator.

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal

clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The

processor will exit idle mode when either an interrupt or a reset occurs.