Preliminary W78LE51

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is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR,

which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses

external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off

again after it has been completely accessed or the program returns to internal ROM code space. The

AO bit in the AUXR register, when set, disables the ALE output. In order to reduce EMI emission from

oscillation circuitry, W78LE51 allows user to diminish the gain of on-chip oscillator amplifiers by using

programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be

decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a

half of gain may effect to external crystal operating improperly at high frequency above 24 MHz. The

value of R and C1,C2 may need some adjustment while running at lower gain.

***AUXR - Auxiliary register (8EH)

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-

-

-

-

-

-

AO

AO: Turn off ALE output.

4. Power-off Flag

***PCON - Power control (87H)

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-

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POF

GF1

GF0

PD

IDL

POF:

Power off flag. Bit is set by hardware when power on reset. It can be cleared by software

to determine chip reset is a warm boot or cold boot.

GF1, GF0: These two bits are general-purpose flag bits for the user.

PD:

Power down mode bit. Set it to enter power down mode.

IDL:

Idle mode bit. Set it to enter idle mode.

be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.

Watchdog Timer

The Watchdog timer is a free-running timer which can be programmed by the user to serve as a

system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide

the system clock. The divider output is selectable and determines the time-out interval. When the

time-out occurs a system reset can also be caused if it is enabled. The main use of the Watchdog

timer is as a system monitor. This is important in real-time control applications. In case of power

glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is

left unchecked the entire system may crash. The watchdog time-out selection will result in different

time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In

general, software should restart the Watchdog timer to put it into a known state. The control bits that

support the Watchdog timer are discussed below.

Watchdog Timer Control Register

Bit:

7

6

5

4

3

2

1

0

ENW

CLRW

WIDL

-

-

PS2

PS1

PS0

Mnemonic: WDTC

Address: 8FH

ENW : Enable watch-dog if set.