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FM28V100 Datasheet(PDF) 2 Page - Cypress Semiconductor |
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FM28V100 Datasheet(HTML) 2 Page - Cypress Semiconductor |
2 / 13 page FM28V100 - 128Kx8 FRAM Rev. 3.0 Apr. 2012 Page 2 of 13 Figure 1. Block Diagram Pin Descriptions Pin Name Type Pin Description A(16:0) Input Address inputs: The 17 address lines select one of 131,072 bytes in the F-RAM array. The address value is latched on the falling edge of /CE1 (while CE2 high) or the rising edge of CE2 (while /CE1 low). Addresses A(2:0) are used for page mode read and write operations. /CE1, CE2 Input Chip Enable inputs: The device is selected and a new memory access begins on the falling edge of /CE1 (while CE2 high) or the rising edge of CE2 (while /CE1 low). The entire address is latched internally at this point. The CE2 pin is pulled up internally. /WE Input Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the FM28V100 to write the data on the DQ bus to the F-RAM array. The falling edge of /WE latches a new column address for fast page mode write cycles. /OE Input Output Enable: When /OE is low, the FM28V100 drives the data bus when valid data is available. Deasserting /OE high tri-states the DQ pins. DQ(7:0) I/O Data: 8-bit bi-directional data bus for accessing the F-RAM array. NC - No Connect: This pin has no internal connection. VDD Supply Supply Voltage VSS Supply Ground Control Logic WE A(16:3) A(2:0) I/O Latch & Bus Driver OE DQ(7:0) A(16:0) Column Decoder . . . CE1, CE2 2 16K x 64 F-RAM Array |
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Similar Description - FM28V100 |
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