W83195R-08

PRELIMINARY

Publication Release Date: Mar. 1999

- 7 -

Revision 0.30

Bytes sequence order for I

Clock Address

A(6:0) & R/W

Ack

8 bits dummy

Command code

Ack

8 bits dummy

Byte count

Ack

Byte0,1,2...

until Stop

Set R/W to 1 when read back the data sequence is as follows [1101 0011] :

Clock Address

A(6:0) & R/W

Ack

Byte 0

Ack

Ack

Byte2, 3, 4...

until Stop

Byte 1

8.3 SERIAL CONTROL REGISTERS

The Pin column lists the affected pin number and the PowerUp column gives the default state at true

power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of

the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must

be sent and will be acknowledge.

After that, the sequence described below (Register 0, Register 1,

Register 2, ....) will be valid and acknowledged.

8.3.1 Register 0: CPU Frequency Select Register (default = 0)

Bit

@PowerUp

Pin

Description

7

0

-

0 = ¡Ó0.25% Spread Spectrum Modulation

1 = ¡Ó0.5% Spread Spectrum Modulation

6

0

-

SSEL2 (for frequency table selection by software via I

5

0

-

SSEL1 (for frequency table selection by software via I

4

0

-

SSEL0 (for frequency table selection by software via I

3

0

-

0 = Selection by hardware

1 = Selection by software I

2

0

-

SSEL3 (for frequency table selection by software via I

1

0

-

0 = Normal

1 = Spread Spectrum enabled

0

0

-

0 = Running

1 = Tristate all outputs

Note : The frequency table selected by software via I

frequency table.