LPC TO ISA BRIDGE SET

W83626F/W83626D

PRELIMINARY

Publication Release Date: Feb 2000

- 5 -

Revision 0.50

LPC Interface, continued

SYMBOL

PIN

I/O

FUNCTION

PWRDN#

24

INtu

Power Down. The signal is active low according to CR 44 Bit 7and

wake-up enable by hardware setting. There are eight different

power-down states (Power down Mode 3).

ISA Interface Signals

SYMBOL

PIN

I/O

FUNCTION

SA[19:17]

58-56

OUT24

System Address Bus. These are the upper address lines that

define the ISA’s byte granular address space (up to 1 M byte).

SA[19:17] are at an unknown state upon PCIRST#.

SA[16:0]

54-51

49-46

44-41

35-31

OUT24

System Address Bus. These are the bi-directional lower address

lines that define the ISA’s byte granular address space (up to 1 M

byte). SA[16:0] are at an unknown state upon PCIRST#.

SD[15:0]

122-1

21

119-1

14

75-71

69-67

OUT24

System Data. SD[15:0] provide the 16-bit data path for devices

residing on the ISA Bus. The W83626F tri-states SD[15:0] during

PCIRST#.

AEN

59

OUT24

Address Enable. AEN is asserted during DMA cycles. This signal

is also driven high during W83626F initiated refresh cycles. AEN is

driven low upon PCIRST#.

IOR#

86

OUT24

I/O Read. IOR# is the command to an ISA I/O slave device that the

slave may drive data on to the ISA data bus (SD[15:0]).

IOW#

84

OUT24

I/O Write. IOW# is the command to an ISA I/O slave device that

the slave may latch data from the ISA data bus (SD[15:0]).

IOCHRDY

61

INt

I/O Channel Ready. Resources on the ISA Bus negate IOCHRDY

to indicate that additional time (wait states) is required to complete

the cycle.

SYSCLK

92

OUT24

ISA System Clock. SYSCLK is the reference clock for the ISA

bus. The SYSCLK is generated by dividing PCICLK by 3 or 4.

RSTDRV

77

OUT24

Reset Drive. W83628F asserts RSTDRV to reset devices that

reside on the ISA Bus. The W83628F asserts this signal while the

PCIRST# is asserted.

IOCS16#

11

INt

16-bit I/O Chip Select. This signal is driven by I/O devices on the

ISA Bus to indicate that they support 16-bit I/O bus cycles.