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W83697SF Datasheet(PDF) 3 Page - Winbond |
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W83697SF Datasheet(HTML) 3 Page - Winbond |
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3 / 128 page  W83697SF PRELIMINARY Publication Release Date: April 2001 - I - Revision 0.50 TABLE OF CONTENT GENERAL DESCRIPTION.............................................................................................................. 1 PIN CONFIGURATION FO R 697SF ................................................................................................ 6 1.0 PIN DESCRIPTION ................................................................................................................ 7 1.1 LPC INTERFACE........................................................................................................................ 7 1.2 FDC INTERFACE........................................................................................................................ 9 1.3 MULTI-MODE PARALLEL PORT.....................................................................................................10 1.4 SERIAL PORT INTERFACE............................................................................................................15 1.5 INFRAREDPORT........................................................................................................................16 1.6 FRESH ROM INTERFACE.............................................................................................................16 1.7 GENERAL PURPOSEI/O PORT .....................................................................................................17 1.8 SMART CARD INTERFACE............................................................................................................17 1.9 PWM & GENERALPURPOSE I/O PORT 8 ...................................................................................... 18 1.10 GAME PORT & MIDI PORT........................................................................................................18 1.11 POWER PINS ...................................................................................................................... 19 2.0 LPC (LOW PIN COUNT) INTERFACE...................................................................................... 20 3.0 FDC FUNCTIONAL DESCRIPTION .........................................................................................21 3.1 W83697SF FDC.....................................................................................................................21 3.1.1 AT interface.....................................................................................................................21 3.1.2 FIFO (Data) .....................................................................................................................21 3.1.3 Data Separator.................................................................................................................22 3.1.4 Write Precompensation.....................................................................................................22 3.1.5 Perpendicular Recording Mode...........................................................................................23 3.1.6 FDC Core ........................................................................................................................23 3.1.7 FDC Commands...............................................................................................................23 3.2 REGISTER DESCRIPTIONS.............................................................................................................36 3.2.1 Status Register A (SA Register) (Read base address + 0) ...................................................36 3.2.2 Status Register B (SB Register) (Read base address + 1) ...................................................38 3.2.3 Digital Output Register (DO Register) (Write base address + 2)............................................40 3.2.4. Tape Drive Register (TD Register) (Read base address + 3)................................................40 3.2.5 Main Status Register (MS Register) (Read base address + 4)...............................................43 3.2.6 Data Rate Register (DR Register) (Write base address + 4) .................................................43 3.2.7 FIFO Register (R/W base address + 5) ..............................................................................45 3.2.8 Digital Input Register (DI Register) (Read base address + 7) ................................................46 3.2.9 Configuration Control Register (CC Register) (Write base address + 7)..................................48 4.0 UART PORT..........................................................................................................................49 |
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