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IS41C16256C Datasheet(PDF) 5 Page - Integrated Silicon Solution, Inc

Part # IS41C16256C
Description  4Mb DRAM WITH EDO PAGE MODE
Download  22 Pages
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS41C16256C Datasheet(HTML) 5 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc.5
Rev. 00A
04/09/2010
IS41C16256C
IS41LV16256C
Functional Description
TheIS41C/LV16256CisaCMOSDRAMoptimizedfor
high-speed bandwidth, low power applications. During
READorWRITEcycles,eachbitisuniquelyaddressed
throughthe18addressbits.Theseareenteredninebits
(A0-A8)atatime.TherowaddressislatchedbytheRow
Address Strobe (RAS).Thecolumnaddressislatchedby
the Column Address Strobe (CAS). RAS is used to latch
the first nine bits and CAS is used the latter nine bits.
TheIS41C/LV16256ChastwoCAS controls, LCAS and
UCAS
.TheLCAS and UCAS inputs internally generates
a CAS signal functioning in an identical manner to the
single CASinputontheother256Kx16DRAMs.Thekey
difference is that each CAS controls its corresponding I/O
tristate logic (in conjunction with OE and WE and RAS).
LCAS
controls I/O0 through I/O7 and UCAS controls I/
O8throughI/O15.
TheIS41C/LV16256CCAS function is determined by the
first CAS (LCAS or UCAS)transitioningLOWandthelast
transitioningbackHIGH.ThetwoCAS controls give the
IS41C/LV16256CbothBYTEREADandBYTEWRITE
cycle capabilities.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it
is terminated by returning both RAS and CAS HIGH.
To ensures proper device operation and data integrity
any memory cycle, once initiated, must not be ended or
aborted before the minimum tras time has expired. A new
cycle must not be initiated until the minimum precharge
time trp, tcp has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or
OE
, whichever occurs last, while holding WEHIGH.The
column address must be held for a minimum time speci-
fied by tar.DataOutbecomesvalidonlywhentrac, taa,
tcac and toea are all satisfied. As a result, the access time
is dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE
,whicheveroccurslast.Theinputdatamustbevalid
at or before the falling edge of CAS or WE, whichever
occurs last.
Refresh Cycle
Toretaindata,512refreshcyclesarerequiredineach
8msperiod.Therearetwowaystorefreshthememory.
1. Byclockingeachofthe512rowaddresses(A0through
A8)withRASatleastonceevery8ms.Anyread,write,
read-modify-write or RAS-only cycle refreshes the ad-
dressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS
refresh is activated by the falling edge of RAS,
while holding CASLOW.InCAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS
-before-RAS is a refresh-only mode and no data
accessordeviceselectionisallowed.Thus,theoutput
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDOpagemodeoperationpermitsall512columnswithin
a selected row to be randomly accessed at a high data
rate.
InEDOpagemodereadcycle,thedata-outisheldtothe
next CAS cycle’s falling edge, instead of the rising edge.
Forthisreason,thevaliddataoutputtimeinEDOpage
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAScycletimebecomesshorter.There-
fore,inEDOpagemode,thetimingmargininreadcycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
InEDOpagemode,duetotheextendeddatafunction,
the CAS cycle time can be shorter than in the fast page
mode if the timing margin is the same.
TheEDOpagemodeallowsbothreadandwriteoperations
during one RAS cycle, but the performance is equivalent
to that of the fast page mode in that case.
Power-On
After application of theVdd supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS
signal).
Duringpower-on,itisrecommendedthatRAS track with
VddorbeheldatavalidVih to avoid current surges.


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