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AD1843JS Datasheet(PDF) 9 Page - Analog Devices |
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AD1843JS Datasheet(HTML) 9 Page - Analog Devices |
9 / 64 page AD1843 REV. 0 –9– Analog Signals Pin Name PQFP TQFP I/O Description LINLP 28 35 I Line Input Left Channel Positive Differential Signal. LINLN 29 36 I Line Input Left Channel Negative Differential Signal. LINRP 26 33 I Line Input Right Channel Positive Differential Signal. LINRN 27 34 I Line Input Right Channel Negative Differential Signal. MICL 18 21 I Microphone Input Left Channel. Microphone input for the left channel. This signal can be either line level or –20 dB from line level. MICR 17 22 I Microphone Input Right Channel. Microphone input for the right channel. This signal can be either line level or –20 dB from line level. AUX1L 16 20 I Auxiliary #1 Left Channel Line Input. AUX1R 15 19 I Auxiliary #1 Right Channel Line Input. AUX2L 14 18 I Auxiliary #2 Left Channel Line Input. AUX2R 13 17 I Auxiliary #2 Right Channel Line Input. AUX3L 12 16 I Auxiliary #3 Left Channel Line Input. AUX3R 11 15 I Auxiliary #3 Right Channel Line Input. MIN 19 23 I Monaural (Mono) Line Input. MOUT 35 44 O Monaural (Mono) Line Output. LOUT1L 36 45 O Line Output #1 Left Channel. LOUT1R 34 43 O Line Output #1 Right Channel. HPOUTL 47 58 O Headphone Output Left Channel. HPOUTC 46 57 Headphone Common Return. HPOUTR 45 56 O Headphone Output Right Channel. LOUT2LP 32 40 O Line Output #2 Left Channel Positive Differential Signal. LOUT2LN 33 41 O Line Output #2 Left Channel Negative Differential Signal. LOUT2RP 30 38 O Line Output #2 Right Channel Positive Differential Signal. LOUT2RN 31 39 O Line Output #2 Right Channel Negative Differential Signal. SUML 43 54 I Mixer Line Input Left Channel. SUMR 42 53 I Mixer Line Input Right Channel. Clocks Pin Name PQFP TQFP I/O Description CLKOUT 76 95 O Clock Output. This signal is a buffered version of XTALO (with a duty cycle restored to at least 60%/40%), the crystal clock output. This pin is enabled by default but can be three-stated by programming a bit in Control Register Address 28. The CLKOUT frequency is 24.576 MHz. SYNC[3:1] 57, 56, 55 71, 70, 69 I Sync Inputs. These SYNC signals are used as the clock source inputs to three receptive PLLs in the AD1843. These pins accept a clock at, or at a multiple of, the desired sample rate for A-to-D and D-to-A conversions. These inputs are ignored if a sample rate is programmed directly, but should never be left floating. CONV[3:1] 75, 71, 67 94, 89, 84 O Conversion Clock Outputs. These output clocks have an average period equal to (or 128 times) the internal sample rates of the AD1843. These clock outputs are three-stated by default but can be enabled by programming bits in Control Register Address 28. BIT[3:1] 74, 70, 66 92, 87, 82 O Bit Clock Outputs. These output clocks can be individually programmed to multiples of the sample rates. Support for V.34 or V.32 bit rates is available. These clock outputs are three-stated by default but can be enabled by programming bits in Control Register Address 28. |
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