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bq24196RGER Datasheet(PDF) 10 Page - Texas Instruments |
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bq24196RGER Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 41 page  bq24196 SLUSB98 – OCTOBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS BOOST MODE OPERATION VOTG_REG OTG output voltage I(VBUS) = 0 5.00 V VOTG_REG_ACC OTG output voltage accuracy I(VBUS) = 0 –2% 2% REG01[0] = 0 0.5 A IOTG OTG mode output current REG01[0] = 1 1.3 A VOTG_OVP OTG over-voltage threshold 5.3 5.5 V VOTG_ILIM LSFET cycle-by-cycle current limit 3.2 4.6 A VOTG_HSZCP HSFET under current falling threshold 100 mA REG01[0] = 1 1.4 1.8 2.7 IRBFET_OCP RBFET over-current threshold A REG01[0] = 0 0.6 1.1 1.8 REGN LDO VVBUS = 10V, IREGN = 40mA 5.6 6 6.4 V VREGN REGN LDO output voltage VVBUS = 5V, IREGN = 20mA 4.75 4.8 4.85 V IREGN REGN LDO current limit VVBUS = 10V, VREGN = 3.8V 50 mA LOGIC I/O PIN CHARACTERISTICS (OTG, CE, PSEL, STAT, PG) VILO Input low threshold 0.4 V VIH Input high threshold 1.3 V VOUT_LO Output low saturation voltage Sink current = 5 mA 0.4 V IBIAS High level leakage current Pull up rail 1.8V 1 µA I2C INTERFACE (SDA, SCL, INT) VIH Input high threshold level VPULL-UP = 1.8V, SDA and SCL 1.3 V VIL Input low threshold level VPULL-UP = 1.8V, SDA and SCL 0.4 V VOL Output low threshold level Sink current = 5mA 0.4 V IBIAS High-level leakage current VPULL-UP = 1.8V, SDA and SCL 1 µA fSCL SCL clock frequency 400 kHz DIGITAL CLOCK AND WATCHDOG TIMER fHIZ Digital crude clock REGN LDO disabled 15 35 50 kHz fDIG Digital clock REGN LDO enabled 1300 1500 1700 kHz tWDT REG05[5:4]=11 REGN LDO enabled 136 160 sec TYPICAL CHARACTERISTICS Table 1. Tables of Figures FIGURE NO. CHARGING EFFICIENCY vs. CHARGING CURRENT Figure 3 SYSTEM LIGHT LOAD EFFICIENCY vs SYSTEM LOAD CURRENT Figure 4 BOOST MODE EFFICIENCY vs VBUS LOAD CURRENT Figure 5 SYS VOLTAGE REGULATION vs SYSTEM LOAD Figure 6 BOOST MODE VBUS VOLTAGE REGULATION vs VBUS LOAD CURRENT Figure 7 SYS VOLTAGE vs TEMPERATURE Figure 8 BAT VOLTAGE vs TEMPERATURE Figure 9 INPUT CURRENT LIMIT vs TEMPERATURE Figure 10 CHARGE CURRENT vs TEMPERATURE Figure 11 Power Up with Charge Disabled (VBAT 3.2V) Figure 12 Power Up with Charge Enabled Figure 13 Charge Enable (VBUS 5V) Figure 14 Charge Disable (VBUS 12V) Figure 15 Input Current DPM Response without Battery (VBUS 5V, IIN 3A, Charge Disable) Figure 16 Load Transient during Supplement Mode (VBUS 9V, IIN 1.5A, VBAT 3.8V) Figure 17 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links :bq24196 |
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