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AD28MSP02BR Datasheet(PDF) 1 Page - Analog Devices |
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AD28MSP02BR Datasheet(HTML) 1 Page - Analog Devices |
1 / 20 page FUNCTIONAL BLOCK DIAGRAM VOICEBAND ANALOG INPUT A VOICEBAND ANALOG INPUT B DIFFERENTIAL ANALOG OUTPUT DIGITAL DATA AND CONTROL SERIAL PORT 16-BIT SIGMA- DELTA DAC 16-BIT SIGMA- DELTA ADC MUX +20dB AMP VOLTAGE REFERENCE PGA REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Voiceband Signal Port One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD28msp02 FEATURES Complete Analog I/O Port for Voiceband DSP Applications Linear-Coded 16-Bit Sigma-Delta ADC Linear-Coded 16-Bit Sigma-Delta DAC On-Chip Anti-Aliasing and Anti-lmaging Filters On-Chip Voltage Reference 8 kHz Sampling Frequency Twos Complement Coding 65 dB SNR + THD Programmable Gain on DAC and ADC Serial Interface To DSP Processors 24-Pin DlP/28-Lead SOIC Single 5 V Power Supply GENERAL DESCRIPTION The AD28msp02 Voiceband Signal Port is a complete analog front end for high performance voiceband DSP applications. Compared to traditional µ-law and A-law codecs, the AD28msp02’s linear-coded ADC and DAC maintain wide dynamic range while maintaining superior SNR and THD. A sampling rate of 8.0 kHz coupled with 65 dB SNR + THD per- formance make the AD28msp02 attractive in many telecom and speech processing applications, for example digital cellular radio and high quality telephones. The AD28msp02 simplifies overall system design by requiring only a single +5 V power supply. The inclusion of on-chip anti-aliasing and anti-imaging filters, 16-bit sigma-delta ADC and DAC, and programmable gain amplifiers ensures a highly integrated and compact solution to voiceband analog processing requirements. Sigma-delta conver- sion technology eliminates the need for complex off-chip anti- aliasing filters and sample-and-hold circuitry. The AD28msp02’s serial I/O port provides an easy interface to host DSP microprocessors such as the ADSP-2101, ADSP-2105 and ADSP-2111. The AD28msp02 is available in a 24-pin, 0.3" plastic DIP and a 28-lead SOIC package. FUNCTIONAL DESCRIPTION Figure 1 shows a block diagram of the AD28msp02. A/D CONVERSION The A/D conversion circuitry of the AD28msp02 consists of two analog input amplifiers, an optional 20 dB preamplifier, and a sigma-delta analog-to-digital converter (ADC). The analog input signal to the AD28msp02 must be ac-coupled. Analog Input Amplifiers The two analog input amplifiers (NORM, AUX) are internally biased by an on-chip voltage reference in order to allow opera- tion of the AD28msp02 with a single +5 V power supply. An analog multiplexer selects either the NORM or AUX ampli- fier as the input to the ADC’s sigma-delta modulator. The optional 20 dB preamplifier may be used to increase the signal level; the preamplifier can be inserted before the modulator or can be bypassed. Input signal level to the sigma-delta modulator should not exceed VINMAX, which is specified under “Analog Interface Electrical Characteristics.” Refer to “Analog Input” in the “Design Considerations” section of this data sheet for more information. The input multiplexer and 20 dB preamplifier are configured by Bits 0 and 1 (IPS, IMS) of the AD28msp02’s control register. If the multiplexer setting is changed while an input signal is being processed, the ADC’s output must be allowed time to settle to ensure that the output data is valid. ADC The ADC consists of a 2nd-order analog sigma-delta modulator, an anti-aliasing decimation filter, and a digital high-pass filter. The sigma-delta modulator noise-shapes the signal and pro- duces 1-bit samples at a 1.0 MHz rate. This bit stream, which represents the analog input signal, is fed to the anti-aliasing decimation filter. Decimation Filter The anti-aliasing decimation filter contains two stages. The first stage is a sinc 4 digital filter that increases resolution to 16 bits and reduces the sample rate to 40 kHz. The second stage is an IIR low-pass filter. |
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