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AD7346B Datasheet(PDF) 6 Page - Analog Devices |
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AD7346B Datasheet(HTML) 6 Page - Analog Devices |
6 / 8 page AD5011 –6– REV PrA PRELIMINARY TECHNICAL DATA PIN DESCRIPTION Mnemonic Function POWER SUPPLY VDRIVE Digital output drive level. AGND Analog power supply. AGND Analog Ground. DVDD Positive power supply for the digital section. DGND Digital Ground. TRANSMIT CHANNEL TxDATA Transmit data input. TxSYNC Transmit data frame synchronization, logic input. TxCLK Transmit serial clock, logic input. TxDECOUP Transmit DAC reference decoupling pin. The reference which supplies the DAC needs some external decoupling. DRV-OUTP Differential line driver positive output. DRV-OUTN Differential line driver negative output. EXTERNAL INTERFACE SPICLK Serial interface clock, logic input. T F S Serial Interface frame synchronisation, logic input. D T Serial interface data input. D R Serial interface data output. RESETB Master Reset. This is an active low logic input. PWRDWNB Master powerdown. When PWRDWNB is taken low, the complete AD5011 device is placed in a sleep mode. FCLK Filter tuning clock. The clock for the filter tuning circuit in both the transmit and receive paths is supplied to FCLK. A 16.384 MHz should be connected to this pin to obtain the specified frequencies. TEST Test Mode. When TEST is tied to DVDD, the AD5011 is placed in a test mode. For normal operation, this pin should be tied to DGND. RECEIVE CHANNEL HYBIN-2B Hybrid non-inverting input. HYBIN-2A Hybrid inverting input. HYBIN-1B Hybrid inverting input. HYBIN-1A Hybrid non-inverting input. FILTOUTP Positive differential output of the antialiasing filter. FILTOUTN Negative differential output of the antialiasing filter. ADCINP Positive differential input to the ADC. ADCINN Negative differential input to the ADC. CAP-T Receive ADC reference decoupling pin. The reference which supplies the ADC needs some external decoupling. CAP-B Receive ADC reference decoupling pin. The reference which supplies the ADC needs some external decoupling. VREF Voltage Reference. The external reference is applied to this pin. REF-COM Reference common. COM-LVL Common mode level. ADCCLK ADC Sample clock, logic input. This clock also operates as the frame synchronization. SCLK ADC serial interface clock, logic input. S D O ADC serial data out. |
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