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AD7346B Datasheet(PDF) 4 Page - Analog Devices |
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AD7346B Datasheet(HTML) 4 Page - Analog Devices |
4 / 8 page AD5011 –4– REV PrA PRELIMINARY TECHNICAL DATA TIMING CHARACTERISTICS (V DD = +2.7 V to +5.5 V; AGND = DGND = 0 V, unless otherwise noted) Limit at TMIN to TMAX Parameter (B Version) Units Test Conditions/Comments ADCCLK <= 1160kHz t1 1.5*t3 ns min ADCCLK Rising Edge to SCLK Rising Edge Delay 2*t3 ns typ t2 2.5*t3 ns min SCLK Rising Edge to ADCCLK Falling Edge Delay 3*t3 ns typ t3 26.939 ns min SCLK Period (1/32*ADCCLK Period) t4 5 ns min Data Setup Time Before SCLK Falling Edge t5 10 ns min Data Hold Time After SCLK Falling Edge 1160 kHz < ADCCLK <= 2320 kHz t6 20 ns min ADCCLK Rising Edge to SCLK Rising Edge Delay 1*t8 ns typ t7 1.5*t8 ns min SCLK Rising Edge to ADCCLK Falling Edge Delay 2*t8 ns typ t8 26.939 ns min SCLK Period (1/16*ADCCLK Period) t9 5 ns min Data Setup Time Before SCLK Falling Edge t10 10 ns min Data Hold Time After SCLK Falling Edge TRANSMIT DAC t11 53.5 ns min TxCLK Period (1/18.688 MHz) t12 12 ns min Data Setup Time Before TxCLK Rising Edge t13 10 ns min Data Hold Time After TxCLK Rising Edge t14 t11 ns min TxSYNC Low Time t15 3 ns min TxCLK Rising Edge to TxSYNC Falling Edge Delay t11/2 ns max CONTROL REGISTER t16 50 ns min SPICLK Period 76 ns typ t17 15 ns min TFS Setup Time Before SPICLK Falling Edge t16 - 15 ns max t18 15 ns min TFS Hold Time After SPICLK Falling Edge t16 - 15 ns max t19 t16 ns typ TFS High Time t20 7 ns min DT Setup Time Before SPICLK Falling Edge t21 10 ns min DT Hold Time After SPICLK Falling Edge t22 7 ns min DR Setup Time Before SPICLK Falling Edge (R/ W = 1) t23 10 ns min DR Hold Time After SPICLK Falling Edge (R/ W = 1) Guaranteed by design but not production tested. D1 1 D1 0 D 1 D0 AD C CL K t 1 t 5 D1 1 D 1 0 D9 SCL K SDO t 2 t 3 t 4 Figure 1. ADC Timing (ADCCLK <= 1160 kHz) SCLK activity and serial output data activity does not coincide with the sesitive ADCCLK clock edges |
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