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A4953 Datasheet(PDF) 7 Page - Allegro MicroSystems

Part # A4953
Description  Designed for pulse width modulated (PWM) control of DC motors, the A4952 and A4953 are capable of peak output currents to 짹2 A and operating voltages to 40 V.
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Manufacturer  ALLEGRO [Allegro MicroSystems]
Direct Link  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

A4953 Datasheet(HTML) 7 Page - Allegro MicroSystems

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Full-Bridge DMOS PWM Motor Drivers
A4952 and
A4953
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Application Information
Sense Pin (LSS)
In order to use PWM current control, a low-value resistor is
placed between the LSS pin and ground for current sensing pur-
poses. To minimize ground-trace IR drops in sensing the output
current level, the current sensing resistor should have an indepen-
dent ground return to the star ground point. This trace should be
as short as possible. For low-value sense resistors, the IR drops in
the PCB can be significant, and should be taken into account.
When selecting a value for the sense resistor be sure not to
exceed the maximum voltage on the LSS pin of ±500 mV at
maximum load. During overcurrent events, this rating may be
exceeded for short durations.
Ground
A star ground should be located as close to the A4952/ A4953
as possible. The copper ground plane directly under the exposed
thermal pad of the device makes a good location for the star
ground point. The exposed pad can be connected to ground for
this purpose.
Layout
The PCB should have a thick ground plane. For optimum electri-
cal and thermal performance, the A4952/A4953 must be soldered
directly onto the board. On the underside of the A4952/A4953
package is an exposed pad, which provides a path for enhanced
thermal dissipation. The thermal pad must be soldered directly to
an exposed surface on the PCB in order to achieve optimal ther-
mal conduction. Thermal vias are used to transfer heat to other
layers of the PCB.
The load supply pin, VBB, should be decoupled with an electro-
lytic capacitor (typically 100 μF) in parallel with a lower valued
ceramic capacitor placed as close as practicable to the device.
GND
RS
GND
GND
GND
C1
BULK
CAPACITANCE
VBB
OUT2
OUT1
C2
VBB
1
PAD
A4952
C1
C2
OUT2
LSS
OUT1
VBB
FLTn
RTRY
IN2
IN1
VREF
GND
RS
PCB
Thermal Vias
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
Thermal (2 oz.
Solder
A4952
Bill of Materials
Item
Reference
Value
Units
Description
1RS
0.25
(for VREF = 5 V, IOUT = 2 A)
Ω
2512, 1 W, 1% or better,
carbon film chip resistor
2
C1
0.22
μF
X5R minimum, 50 V or greater
3
C2
100
μF
Electrolytic, 50 V or greater
Layout for the A4952 (LY package)


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