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AD5311BRM Datasheet(PDF) 3 Page - Analog Devices

Part # AD5311BRM
Description  2.5 V to 5.5 V, 120 uA, 2-Wire Interface, Voltage Output 8-/10-/12-Bit DACs
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5311BRM Datasheet(HTML) 3 Page - Analog Devices

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REV. 0
AD5301/AD5311/AD5321
–3–
AC CHARACTERISTICS1
B Version3
Parameter2
Min
Typ
Max
Units
Conditions/Comments
Output Voltage Settling Time
VDD = +5 V
AD5301
6
8
µs
1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex)
AD5311
7
9
µs
1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex)
AD5321
8
10
µs
1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex)
Slew Rate
0.7
V/
µs
Major-Code Change Glitch Impulse
12
nV-s
1 LSB Change Around Major Carry
Digital Feedthrough
0.3
nV-s
NOTES
1See Terminology
2Guaranteed by design and characterization, not production tested.
3Temperature ranges are as follows: B Version: –40
°C to +105°C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1
Limit at TMIN, TMAX
Parameter2
(B Version)
Units
Conditions/Comments
fSCL
400
kHz max
SCL Clock Frequency
t1
2.5
µs min
SCL Cycle Time
t2
0.6
µs min
tHIGH, SCL High Time
t3
1.3
µs min
tLOW, SCL Low Time
t4
0.6
µs min
tHD,STA, Start/Repeated Start Condition Hold Time
t5
100
ns min
tSU,DAT, Data Setup Time
t6
3
0.9
µs max
tHD,DAT, Data Hold Time
0
µs min
t7
0.6
µs min
tSU,STA, Setup Time for Repeated Start
t8
0.6
µs min
tSU,STO, Stop Condition Setup Time
t9
1.3
µs min
tBUF, Bus Free Time Between a STOP Condition and a START Condition
t10
300
ns max
tR, Rise Time of Both SCL and SDA when Receiving
0
ns min
May be CMOS Driven
t11
250
ns max
tF, Fall Time of SDA when Receiving
300
ns max
tF, Fall Time of Both SCL and SDA when Transmitting
20 + 0.1Cb
4
ns min
Cb
400
pF max
Capacitive Load for Each Bus Line
NOTES
1See Figure 1.
2Guaranteed by design and characterization, not production tested.
3A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH MIN of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
4C
b is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
Specifications subject to change without notice.
(VDD = +2.5 V to +5.5 V; RL = 2 k
Ω to GND; C
L = 200 pF to GND; All specifications TMIN to TMAX unless
otherwise noted.)
(VDD = +2.5 V to +5.5 V. All specifications TMIN to TMAX unless otherwise noted.)


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