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AD5301 Datasheet(HTML) 7 Page - Analog Devices

Part No. AD5301
Description  2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5301 Datasheet(HTML) 7 Page - Analog Devices

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REV. 0
AD5330/AD5331/AD5340/AD5341
–7–
AD5340 FUNCTIONAL BLOCK DIAGRAM
BUFFER
12-BIT
DAC
DAC
REGISTER
INPUT
REGISTER
INTER-
FACE
LOGIC
POWER-DOWN
LOGIC
BUF
GAIN
DB11
DB0
..
CS
WR
CLR
LDAC
VREF
VDD
VOUT
PD
GND
AD5340
POWER-ON
RESET
RESET
AD5340 PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1DB10
Parallel Data Input.
2DB11
Most Significant Bit of Parallel Data Input.
3
BUF
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
4VREF
Reference Input.
5VOUT
Output of DAC. Buffered output with rail-to-rail operation.
6
NC
No Connect.
7
GND
Ground reference point for all circuitry on the part.
8
CS
Active Low Chip Select Input. This is used in conjunction with
WR to write data to the parallel interface.
9
WR
Active Low Write Input. This is used in conjunction with
CS to write data to the parallel interface.
10
GAIN
Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF.
11
CLR
Asynchronous active low control input that clears all input registers and DAC registers to zero.
12
LDAC
Active low control input that updates the DAC registers with the contents of the input registers.
13
PD
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
14
VDD
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled
with a 10
µF capacitor in parallel with a 0.1 µF capacitor to GND.
15–24
DB0–DB9
10 Parallel Data Inputs.
AD5340 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD5340
LDAC
GAIN
WR
CS
DB10
VOUT
GND
PD
VDD
DB0
DB1
DB2
DB7
DB6
DB3
DB4
DB5
12-BIT
VREF
BUF
CLR
DB8
DB9
NC
NC = NO CONNECT
DB11


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