AD569

REV. A

–5–

Figure 3. AD569 Block Diagram

FUNCTIONAL DESCRIPTION

The AD569 consists of two resistor strings, each of which is di-

vided into 256 equal segments (see Figure 3). The 8 MSBs of

the digital input word select one of the 256 segments on the first

string. The taps at the top and bottom of the selected segment

are connected to the inputs of the two buffer amplifiers A1 and

A2. These amplifiers exhibit extremely high CMRR and low

bias current, and thus accurately preserve the voltages at the top

and bottom of the segment. The buffered voltages from the seg-

ment endpoints are applied across the second resistor string,

where the 8LSBs of the digital input word select one of the 256

taps. Output amplifier A3 buffers this voltage and delivers it to

the output.

Buffer amplifiers A1 and A2 leap-frog up the first string to pre-

serve monotonicity at the segment boundaries. For example,

segment boundary), A1 remains connected to the same tap on

the first resistor, while A2 jumps over it and is connected to the

tap which becomes the top of the next segment. This design

guarantees monotonicity even if the amplifiers have offset volt-

ages. In fact, amplifier offset only contributes to integral linear-

ity error.

CAUTION

It is generally considered good engineering practice to avoid

inserting integrated circuits into powered-up sockets. This

guideline is especially important with the AD569. An empty,

powered-up socket configures external buffer amplifiers in an

open-loop mode, forcing their outputs to be at the positive or

negative rail. This condition may result in a large current surge

between the reference force and sense terminals. This current

surge may permanently damage the AD569.

ANALOG CIRCUIT DETAILS

MONOTONICITY: A DAC is monotonic if the output either

increases or remains constant for increasing digital inputs. All

versions of the AD569 are monotonic over their full operating

temperature range.

DIFFERENTIAL NONLINEARITY: DNL is the measure of

the change in the analog output, normalized to full scale, associ-

ated: with a 1 LSB change in the digital input code. Monotonic

behavior requires that the differential linearity error be less than

1 LSB over the temperature range of interest. For example, for a

±5 V output range, a change of 1 LSB in digital input code

should result in a 152

µV change in the analog output (1 LSB =

10 V/65,536). If the change is actually 38

µV, however, the dif-

ferential linearity error would be –114

µV, or –3/4 LSB. By leap-

frogging the buffer amplifier taps on the first divider, a typical

AD569 keeps DNL within

±38 µV (±1/4 LSB) around each of

the 256 segment boundaries defined by the upper byte of the in-

put word (see Figure 5). Within the second divider, DNL also

typically remains less than

±38 µV as shown in Figure 6. Since

the second divider is independent of absolute voltage, DNL is

the same within the rest of the 256 segments.

OFFSET ERROR: The difference between the actual analog

all zeros is called the offset error. For the AD569, Unipolar Off-

BIPOLAR ZERO ERROR: The deviation of the analog output

from the ideal half-scale output of 0.0000 V when the inputs are

AD569, it is specified with

±5 V applied to the reference

terminals.

Definitions

LINEARITY ERROR: Analog Devices defines linearity error as

the maximum deviation of the actual, adjusted DAC output

from the ideal output (a straight line drawn from 0 to FS–1LSB)

for any bit combination. The AD569’s linearity is primarily lim-

ited by resistor uniformity in the first divider (upper byte of

16-bit input). The plot in Figure 4 shows the AD569’s typical

linearity error across the entire output range to be within

±0.01% of full scale. At 25°C the maximum linearity error for

the AD569JN, AD and SD grades is specified to be

±0.04%,

and

±0.024% for the KN and BD versions.

Figure 4. Typical Linearity