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AD679JD Datasheet(PDF) 11 Page - Analog Devices |
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AD679JD Datasheet(HTML) 11 Page - Analog Devices |
11 / 12 page AD679 REV. C –11– The following examples illustrate typical AD679 interface configurations. AD679 to TMS320C25 In Figure 9 the AD679 is mapped into the TMS320C25 I/O space. AD679 conversions are initiated by issuing an OUT in- struction to Port 1. EOC status and the conversion result are read in with an IN instruction to Port 1. A single wait state is in- serted by generating the processor READY input from IS, Port 1 and MSC. Address line A0 provides HBE decoding to select between the high and low bytes of data. This configuration sup- ports processor clock speeds of 20 MHz and is capable of sup- porting processor clock speeds of 40 MHz if a NOP instruction follows each AD679 read instruction. Figure 9. AD679 to TMS320C25 Interface AD679 to 80186 Figure 10 shows the AD679 interfaced to the 80186 micropro- cessor. This interface allows the 80186’s built-in DMA control- ler to transfer the AD679 output into a RAM based FIFO buffer of any length, with no microprocessor intervention. In this application the AD679 is configured in the asynchronous mode, which allows conversions to be initiated by an external trigger source independent of the microprocessor clock. After each conversion, the AD679 EOC signal generates a DMA re- quest to Channel 1 (DRQ1). The subsequent DMA READ se- quences the high and low byte AD679 data and resets the interrupt latch. The system designer must assign a sufficient pri- ority to the DMA channel to ensure that the DMA request will be serviced before the completion of the next conversion. This configuration can be used with 6 MHz and 8 MHz 80186 processors. Figure 10. AD679 to 80186 DMA Interface AD679 to Analog Devices ADSP-2101 Figure 11 demonstrates the AD679 interfaced to an ADSP-2101. With a clock frequency of 12.5 MHz, and instruction execution in one 80 ns cycle, the digital signal processor supports the AD679 interface with one wait state. The converter is configured to run asynchronously using a sam- pling clock. The EOC output of the AD679 gets asserted at the end of each conversion and causes an interrupt. Upon interrupt, the ADSP-2101 immediately asserts its FO pin LOW. In the following cycle, the processor starts a data memory read by pro- viding an address on the DMA bus. The decoded address gener- ates OE for the converter, and the high byte of the conversion result is read over the data bus. The read operation is extended with one wait state and thus started and completed within two processor cycles (160 ns). Next, the ADSP-2101 asserts its FO HIGH. This allows the processor to start reading the lower byte of data. This read operation executes in a similar manner to the first and is completed during the next 160 ns. Figure 11. AD679 to ADSP-2101 Interface AD679 to Analog Devices ADSP-2100A Figure 12 demonstrates the AD679 interfaced to an ADSP-2100A. With a clock frequency of 12.5 MHz, and instruction execution in one 80 ns cycle, the digital signal processor will support theAD679 data memory interface with three hardware wait states. The converter is configured to run asynchronously using a sam- pling clock. The EOC output of the AD679 gets asserted at the end of each conversion and causes an interrupt. Upon interrupt, the ADSP-2100A immediately executes a data memory write in- struction which asserts HBE. In the following cycle, the proces- sor starts a data memory read (high byte read) by providing an address on the DMA bus. The decoded address generates OE for the converter. OE, together with logic and latch, is used to force the ADSP-2100A into a one cycle wait state by generating DMACK. The read operation is thus started and completed within two processor cycles (160 ns). HBE is released during “high byte read.” This allows the processor to read the lower byte of data as soon as “high byte read” is complete. The low byte read operation executes in a similar manner to the first and is completed during the next 160 ns. Figure 12. AD679 to ADSP-2100A Interface |
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