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AD7249BR Datasheet(PDF) 4 Page - Analog Devices |
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AD7249BR Datasheet(HTML) 4 Page - Analog Devices |
4 / 12 page REV. C –4– AD7249 PIN FUNCTION DESCRIPTION (DIP & SOIC PIN NUMBERS) Pin Mnemonic Description 11 REFOUT Voltage Reference Output. The internal 5 V analog reference is provided at this pin. To operate the part using its internal reference, REFOUT should be connected to REFIN. 12 REFIN Voltage Reference Input. It is internally buffered before being applied to both DACs. The nominal reference voltage for specified operation of the AD7249 is 5 V. 13ROFSB Output Offset Resistor for the amplifier of DAC B. It is connected to VOUTB for the +5 V range, to AGND for the +10 V range and to REFIN for the –5 V to +5 V range. 14VOUTB Analog Output Voltage of DAC B. This is the buffer amplifier output voltage. Three different output voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and –5 V to +5 V. 15 AGND Analog Ground. Ground reference for all analog circuitry. 16 CLR Clear, Logic Input. Taking this input low clears both DACs. It sets VOUTA and VOUTB to 0 V in both unipolar ranges and the twos complement bipolar range and to –REFIN in the offset binary bipolar range. 17 BIN/COMP Logic Input. This input selects the data format to be either binary or twos complement. In both uni- polar ranges natural binary format is selected by connecting this input to a Logic “0”. In the bipolar configuration offset binary format is selected with a Logic “0” while a Logic “1” selects twos complement. 18 DGND Digital Ground. Ground reference for all digital circuitry. 19 SDIN Serial Data In, Logic Input. The 16-bit serial data word is applied to this input. 10 LDAC Load DAC, Logic Input. Updates both DAC outputs. The DAC outputs are updated on the falling edge of this signal or alternatively if this line is permanently low, an automatic update mode is se- lected whereby both DACs are updated on the 16th falling SCLK pulse. 11 SCLK Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge. 12 SYNC Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in readi- ness for a new data word. 13 VDD Positive Power Supply. 14 VOUTA Analog Output Voltage of DAC A. This is the buffer amplifier output voltage. Three different output voltage ranges can be chosen: 0 V to +5 V, 0 V to +10 V and –5 V to +5 V. 15 VSS Negative Power Supply (used for the output amplifier only) may be connected to 0 V for single sup- ply operation or –12 V to –15 V for dual supplies. 16 ROFSA Output Offset Resistor for the amplifier of DAC A. It is connected to VOUTA for the +5 V range, to AGND for the +10 V range and to REFIN for the –5 V to +5 V range. PIN CONFIGURATIONS (DIP and SOIC) TOP VIEW (Not to Scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 REFOUT ROFSA AD7249 REFIN VSS ROFSB VOUTA VOUTB VDD AGND SYNC CLR SCLK BIN/COMP LDAC DGND SDIN ORDERING GUIDE Temperature Relative Package Model Range Accuracy Option AD7249AN –40 °C to +85°C ±1 LSB N-16 AD7249BN –40 °C to +85°C ±1/2 LSB N-16 AD7249AR –40 °C to +85°C ±1 LSB R-16 AD7249BR –40 °C to +85°C ±1/2 LSB R-16 AD7249SQ 1 –55 °C to +125°C ±1 LSB Q-16 NOTE 1Available to /883B processing only. Contact your local sales office for military data sheet. |
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