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AD7304BN Datasheet(PDF) 6 Page - Analog Devices

Part # AD7304BN
Description  3 V/5 V, Rail-to-Rail Quad, 8-Bit DAC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7304BN Datasheet(HTML) 6 Page - Analog Devices

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AD7304/AD7305
–6–
REV. A
AD7304 PIN FUNCTION DESCRIPTIONS
Pin #
Name
Function
1VOUTB
Channel B rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REFB pin. Output
is open circuit when SHDN is enabled.
2VOUTA
Channel A rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REFA pin. Output
is open circuit when SHDN is enabled.
3VSS
Negative Power Supply Input. Specified range of operation 0 V to –5.5 V.
4VREFA
Channel A Reference Input. Establishes VOUTA full-scale voltage. Specified range of operation VSS < VREFA < VDD.
5VREFB
Channel B Reference Input. Establishes VOUTB full-scale voltage. Specified range of operation VSS < VREFB < VDD.
6
GND
Common Analog and Digital Ground.
7
LDAC
Load DAC register strobe, active low. Transfers all four Input Register data into their DAC registers. Asynchronous
active low input. DAC Register is transparent when LDAC = 0. See Control Logic Truth Table for operation.
8
CLR
Clears all Input and DAC registers to the zero condition. Asynchronous active low input. The serial register is not effected .
9
CS
Chip Select, Active Low Input. Disables shift register loading when high. Transfers Serial Input Register Data to the
decoded Input Register when CS returns HIGH. Does not effect LDAC operation.
10
CLK
Clock input, positive edge clocks data into shift register. Disabled by chip select CS.
11
SDI/SHDN
Serial Data-Input loads directly into the shift register, MSB first. Hardware shutdown (SHDN) control input, active
when pin is left floating by a three-state logic driver. Does not effect DAC register contents as long as power is
present on VDD.
12
VREFD
Channel D Reference Input. Establishes VOUTD full-scale voltage. Specified range of operation VSS < VREFD < VDD.
13
VREFC
Channel C Reference Input. Establishes VOUTC full-scale voltage. Specified range of operation VSS < VREFC < VDD.
14
VDD
Positive power supply input. Specified range of operation +2.7 V to +5.5 V.
15
VOUTD
Channel D rail-to-rail buffered DAC voltage output. Full-scale set by reference voltage applied to V REFD pin. Output
is open circuit when SHDN is enabled.
16
VOUTC
Channel C rail-to-rail buffered DAC voltage output. Full-scale set by reference voltage applied to V REFC pin. Output
is open circuit when SHDN is enabled.
AD7305 PIN FUNCTION DESCRIPTIONS
Pin #
Name
Function
1VOUTB
Channel B rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REFB pin. Output
is open circuit when SHDN is enabled.
2VOUTA
Channel A rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REFA pin. Output
is open circuit when SHDN is enabled.
3VSS
Negative Power Supply Input. Specified range of operation 0 V to –5.5 V.
4VREF
Channel B Reference Input. Establishes VOUT full-scale voltage. Specified range of operation VSS < VREF < VDD.
5
GND
Common Analog and Digital Ground.
6
LDAC
Load DAC register strobe, active low. Transfers all four Input Register data into their DAC registers. Asynchronous
active low input. DAC Register is transparent when LDAC = 0. See Control Logic Truth Table for operation.
7
DB7
MSB Digital Input Data Bit.
8
DB6
Data Bit 6.
9
DB5
Data Bit 5.
10
DB4
Data Bit 4.
11
DB3
Data Bit 3.
12
DB2
Data Bit 2.
13
DB1
Data Bit 1.
14
DB0
LSB Digital Input Data Bit.
15
WR
Write data into Input Register control line, active low. See Control Logic Truth Table for operation.
16
A1
Address Bit 1.
17
A0/SHDN
Address Bit 0/Hardware shutdown (SHDN) control input, active when pin is left floating by a three-state logic driver.
Does not effect DAC register contents as long as power is present on VDD.
18
VDD
Positive Power Supply Input. Specified range of operation +2.7 V to +5.5 V.
19
VOUTD
Channel D rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to V REFD pin. Output
is open circuit when SHDN is enabled.
20
VOUTC
Channel C rail-to-rail buffered DAC voltage output. Full scale set by reference voltage applied to VREFC pin. Output
is open circuit when SHDN is enabled.


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