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AD7339 Datasheet(PDF) 4 Page - Analog Devices |
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AD7339 Datasheet(HTML) 4 Page - Analog Devices |
4 / 12 page AD7339 –4– REV. 0 TIMING CHARACTERISTICS Limit at Parameter TA = –40 C to +85 C Units Description ADC See Figure 3. t1 480 ns min ADCCLK Period t2 210 ns min ADCCLK Width Low t3 210 ns min ADCCLK Width High t4 100 ns min Data Valid After Falling Edge of ADCCLK t5 200 ns min Data Valid Before Subsequent Falling Edge of ADCCLK PARALLEL DACS See Figure 4. t6 430 ns min DACCLK Period t7 200 ns min DACCLK Width Low t8 200 ns min DACCLK Width High t9 130 ns min Data Setup Before DACCLK Rising Edge Time t10 50 ns min Data Hold After DACCLK Rising Edge Time t11 150 ns max Propagation Delay t12 250 ns max Settling Time (from 10% to 90%) SERIAL DACS See Figure 5. t13 3.9 µs min SCLK Period t14 1.94 µs min SCLK Width Low t15 1.94 µs min SCLK Width High t16 950 ns min Data Setup Before SCLK Rising Edge t17 950 ns min Latch Enable Setup Time After SCLK Falling Edge t18 480 ns min LATCH Pulsewidth t19 100 µs max Conversion Delay (AVDD = +5 V 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise noted) +2.1V 2mA CL 15pF IOH TO OUTPUT PIN IOL 1mA Figure 2. Load Circuit for Timing Specifications |
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