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AD73422BB-40 Datasheet(PDF) 5 Page - Analog Devices |
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AD73422BB-40 Datasheet(HTML) 5 Page - Analog Devices |
5 / 36 page REV. 0 –5– AD73422 POWER CONSUMPTION Conditions Typ Max SE AMCLK On Test Conditions AFE SECTION ADCs Only On 11.5 12 1 YES REFOUT Disabled DACs Only On 20 22 1 YES REFOUT Disabled ADCs and DACs On 24.5 27 1 YES REFOUT Disabled ADCs and DACs and Input Amps On 30 34 1 YES REFOUT Disabled ADCs and DACs and AGT On 29 32.5 1 YES REFOUT Disabled All Sections On 37 43.5 1 YES REFCAP Only On 0.8 1.25 0 NO REFOUT Disabled REFCAP and REFOUT Only On 3.5 4.75 0 NO All AFE Sections Off 1.5 3.0 0 YES AMCLK Active Levels Equal to 0 V and DVDD All AFE Sections Off 10 µA 40 µA 0 NO Digital Inputs Static and Equal to 0 V or DVDD NOTES The above values are in mA and are typical values unless otherwise noted. Specifications subject to change without notice. TIMING CHARACTERISTICS–AFE SECTION1 Parameter Limit Units Description Clock Signals See Figure 1 t1 61 ns min 16.384 MHz AMCLK Period t2 24.4 ns min AMCLK Width High t3 24.4 ns min AMCLK Width Low Serial Port See Figures 3 and 4 t4 t1 ns min SCLK Period (SCLK = AMCLK) t5 0.4 × t1 ns min SCLK Width High t6 0.4 × t1 ns min SCLK Width Low t7 20 ns min SDI/SDIFS Setup Before SCLK Low t8 0 ns min SDI/SDIFS Hold After SCLK Low t9 10 ns max SDOFS Delay from SCLK High t10 10 ns min SDOFS Hold After SCLK High t11 10 ns min SDO Hold After SCLK High t12 10 ns max SDO Delay from SCLK High t13 30 ns max SCLK Delay from AMCLK NOTES 1For details of the DSP section timing, please refer to the ADSP-2185L data sheet and the ADSP-2100 Family User’s Manual, Third Edition. Specifications subject to change without notice. |
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