REV. 0

AD73460

–8–

PIN FUNCTION DESCRIPTIONS

1

Mnemonic

Function

VINP1

Analog Input to the Positive Terminal of Input Channel 1.

VINN1

Analog Input to the Negative Terminal of Input Channel 1.

VINP2

Analog Input to the Positive Terminal of Input Channel 2.

VINN2

Analog Input to the Negative Terminal of Input Channel 2.

VINP3

Analog Input to the Positive Terminal of Input Channel 3.

VINN3

Analog Input to the Negative Terminal of Input Channel 3.

VINP4

Analog Input to the Positive Terminal of Input Channel 4.

VINN4

Analog Input to the Negative Terminal of Input Channel 4.

VINP5

Analog Input to the Positive Terminal of Input Channel 5.

VINN5

Analog Input to the Negative Terminal of Input Channel 5.

VINP6

Analog Input to the Positive Terminal of Input Channel 6.

VINN6

Analog Input to the Negative Terminal of Input Channel 6.

REFOUT

Buffered Reference Output, which has a nominal value of 1.25 V.

REFCAP

A Bypass Capacitor to AGND2 of 0.1

µF is required for the on-chip reference. The capacitor should be fixed

to this pin. This pin can be overdriven by an external reference if required.

AVDD

Analog Power Supply Connection

AGND

Analog Ground/Substrate Connection

DGND

Digital Ground/Substrate Connection

DVDD

Digital Power Supply Connection

ARESET

Active Low Reset Signal. This input resets the analog front end of the AD73460, resetting the control registers and

clearing the digital circuitry.

SCLK2

Output Serial Clock whose rate determines the serial transfer rate to/from the AFE. It is used to clock data or

control information to and from the serial port (SPORT2). The frequency of SCLK is equal to the frequency

of the master clock (MCLK) divided by an integer number—this integer number being the product of the

external master clock rate divider and the serial clock rate divider.

MCLK

Master Clock Input of the analog front end. MCLK is driven from an external clock signal.

SDO

Serial Data Output of the AD73460. Both data and control information may be output on this pin and are clocked

on the positive edge of SCLK2. SDO is in three-state when no information is being transmitted and when SE is low.

SDOFS

Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active one SCLK period

before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK2. SDOFS is in

three-state when SE is low.

SDIFS

Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and it is valid one SCLK period before

the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK2 and is ignored when SE

is low.

SDI

Serial Data Input of the AD73460. Both data and control information may be input on this pin and are clocked on

the negative edge of SCLK2. SDI is ignored when SE is low.

SE

SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins

of the SPORT are three-stated and the input pins are ignored. SCLK2 is also disabled internally in order to

decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are

at their original values (before SE was brought low); however, the timing counters and other internal registers are

at their reset values.

RESET

(Input) Processor Reset Input

BR

(Input) Bus Request Input

BG

(Output) Bus Grant Output

BGH

(Output) Bus Grant Hung Output

DMS

(Output) Data Memory Select Output

PMS

(Output) Program Memory Select Output

IOMS

(Output) Memory Select Output

BMS

(Output) Byte Memory Select Output

CMS

(Output) Combined Memory Select Output

RD

(Output) Memory Read Enable Output