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AD7391ARU Datasheet(PDF) 3 Page - Analog Devices |
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AD7391ARU Datasheet(HTML) 3 Page - Analog Devices |
3 / 12 page SPECIFICATIONS AD7391 ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions 3 V 10% 5 V 10% Units STATIC PERFORMANCE Resolution 1 N 10 10 Bits Relative Accuracy 2 INL TA = 25 °C 1.75 1.75 LSB max Relative Accuracy 2 INL TA = 40 °C, 85°C, 125°C 2.0 2.0 LSB max Differential Nonlinearity 2 DNL Monotonic 0.9 0.9 LSB max Zero-Scale Error VZSE Data = 000H 9.0 9.0 mV max Full-Scale Voltage Error VFSE TA = 25 °C, 85°C, 125°C, 32 32 mV max Data = 3FFH Full-Scale Voltage Error VFSE TA = 40 °C, Data = 3FF H 35 35 mV max Full-Scale Tempco 3 TCVFS 16 16 ppm/ °C typ REFERENCE INPUT VREF IN Range VREF 0/VDD 0/VDD V min/max Input Resistance RREF 2.5 2.5 M Ω typ4 Input Capacitance 3 CREF 5 5 pF typ ANALOG OUTPUT Output Current (Source) IOUT Data = 800H, ∆V OUT = 5 LSB 1 1 mA typ Output Current (Sink) IOUT Data = 800H, ∆V OUT = 5 LSB 3 3 mA typ Capacitive Load3 CL No Oscillation 100 100 pF typ LOGIC INPUTS Logic Input Low Voltage VIL 0.5 0.8 V min Logic Input High Voltage VIH VDD 0.6 VDD 0.6 V max Input Leakage Current IIL 10 10 µA max Input Capacitance3 CIL 10 10 pF max INTERFACE TIMING 3, 5 Clock Width High tCH 50 30 ns Clock Width Low tCL 50 30 ns Load Pulse Width tLDW 30 20 ns Data Setup tDS 10 10 ns Data Hold tDH 30 15 ns Clear Pulse Width tCLRW 15 15 ns Load Setup tLD1 30 15 ns Load Hold tLD2 40 20 ns AC CHARACTERISTICS6 Output Slew Rate SR Data = 000H to 3FFH to 000H 0.05 0.05 V/ µs typ Settling Time tS To 0.1% of Full Scale 70 60 µs typ DAC Glitch Q Code 7FFH to 800H to 7FFH 65 65 nVs typ Digital Feedthrough Q 15 15 nVs typ Feedthrough VOUT/VREF VREF = 1.5 VDC 1 V p-p, 63 63 dB typ Data = 000H, f = 100 kHz SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE DNL < 1 LSB 2.7/5.5 2.7/5.5 V min/max Positive Supply Current IDD VIL = 0 V, No Load, TA = 25 °C55 55 µA typ Positive Supply Current IDD VIL = 0 V, No Load 100 100 µA max Power Dissipation PDISS VIL = 0 V, No Load 300 500 µW max Power Supply Sensitivity PSS ∆V DD = 5% 0.003 0.006 %/% max NOTES 1One LSB = V REF/1024 V for the 10-bit AD7391. 2The first two codes (000 H, 001H) are excluded from the linearity error measurement. 3These parameters are guaranteed by design and not subject to production testing. 4Typicals represent average readings measured at 25 °C. 5All input control signals are specified with t R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.6 V. 6The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground. Specifications subject to change without notice. (@ VREF IN = 2.5 V, 40 C < TA < 85 C, unless otherwise noted) AD7390/AD7391 REV. 0 –3– |
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