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AD7376ARU100 Datasheet(PDF) 3 Page - Analog Devices |
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AD7376ARU100 Datasheet(HTML) 3 Page - Analog Devices |
3 / 12 page –3– REV. 0 AD7376 ORDERING GUIDE Temperature Package Package Model k Range Description Options AD7376AN10 10 –40 °C to +85°C PDIP-14 N-14 AD7376AR10 10 –40 °C to +85°C SOL-16 R-16 AD7376ARU10 10 –40 °C to +85°C TSSOP-14 RU-14 AD7376AN50 50 –40 °C to +85°C PDIP-14 N-14 AD7376AR50 50 –40 °C to +85°C SOL-16 R-16 AD7376ARU50 50 –40 °C to +85°C TSSOP-14 RU-14 AD7376AN100 100 –40 °C to +85°C PDIP-14 N-14 AD7376AR100 100 –40 °C to +85°C SOL-16 R-16 AD7376ARU100 100 –40 °C to +85°C TSSOP-14 RU-14 AD7376AN1M 1,000 –40 °C to +85°C PDIP-14 N-14 AD7376AR1M 1,000 –40 °C to +85°C SOL-16 R-16 AD7376ARU1M 1,000 –40 °C to +85°C TSSOP-14 RU-14 Die Size: 101.6 mil × 127.6 mil, 2.58 mm × 3.24 mm Number Transistors: 840 NOTES 11Typicals represent average readings at +25 °C, V DD = +15 V, and VSS = –15 V. 12Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27. Test Circuit. 13INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 26. Test Circuit. 14Resistor terminals A, B, W have no limitations on polarity with respect to each other. 15Guaranteed by design and not subject to production test. 16Measured at the A terminal. A terminal is open circuit in shutdown mode. 17I OL = 200 µA for the 50 kΩ version operating at VDD = +5 V. 18P DISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 19Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band- width. The highest R value results in the minimum overall power consumption. 10All dynamic characteristics use V DD = +15 V and VSS = –15 V. 11See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using both V DD = +5 V or +15 V. 12Propagation delay depends on value of V DD, RL and CL see Applications section. Specifications subject to change without notice. WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7376 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS (TA = +25°C, unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +30 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –16.5 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +44 V VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD AX – BX, AX – WX, BX – WX . . . . . . . . . . . . . . . . . . . ±20 mA Digital Input Voltages to GND . . . . . . . . . . 0 V, VDD + 0.3 V Digital Output Voltage to GND . . . . . . . . . . . . . . 0 V, +30 V Operating Temperature Range . . . . . . . . . . . –40 °C to +85°C Maximum Junction Temperature (TJ MAX) . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65 °C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300 °C Package Power Dissipation . . . . . . . . . . . . (TJ MAX – TA)/θJA Thermal Resistance θ JA P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 °C/W SOIC (SOL-16) . . . . . . . . . . . . . . . . . . . . . . . . . . 120 °C/W TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 °C/W PIN CONFIGURATIONS PDIP & TSSOP-14 SOL-16 14 13 12 11 10 9 8 1 2 3 4 7 6 5 TOP VIEW (Not to Scale) NC = NO CONNECT AD7376 W NC VDD SDO SHDN SDI NC A B VSS GND CS RS CLK 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 TOP VIEW (Not to Scale) AD7376 NC = NO CONNECT W NC VDD SDO SDI NC NC A B VSS GND CLK NC SHDN CS RS |
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