Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

AD7450ARM Datasheet(PDF) 3 Page - Analog Devices

Part # AD7450ARM
Description  Differential Input, 1MSPS, 12-Bit ADC in 關SO-8 and S0-8
Download  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7450ARM Datasheet(HTML) 3 Page - Analog Devices

  AD7450ARM Datasheet HTML 1Page - Analog Devices AD7450ARM Datasheet HTML 2Page - Analog Devices AD7450ARM Datasheet HTML 3Page - Analog Devices AD7450ARM Datasheet HTML 4Page - Analog Devices AD7450ARM Datasheet HTML 5Page - Analog Devices AD7450ARM Datasheet HTML 6Page - Analog Devices AD7450ARM Datasheet HTML 7Page - Analog Devices AD7450ARM Datasheet HTML 8Page - Analog Devices AD7450ARM Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 24 page
background image
REV. PrJ
PRELIMINARY TECHNICAL DATA
–3–
Limit at TMIN, TMAX
Parameter
+3V
+5V
Units
Description
fSCLK
4
10
10
kHz min
15
18
MHz max
tCONVERT
16 x tSCLK
16 x tSCLK
tSCLK = 1/fSCLK
1.07
0.88
µs max
SCLK = 15MHz, 18MHz
tQUIET
50
50
ns min
Minimum Quiet Time between the End of a Serial Read and the
Next Falling Edge of
CS
t1
10
10
ns min
Minimum
CS Pulsewidth
t2
10
10
ns min
CS falling Edge to SCLK Falling Edge Setup Time
t3
5
20
20
ns max
Delay from
CS Falling Edge Until SDATA 3-State Disabled
t4
5
40
40
ns max
Data Access Time After SCLK Falling Edge
t5
0.4 tSCLK
0.4 tSCLK
ns min
SCLK High Pulse Width
t6
0.4 tSCLK
0.4 tSCLK
ns min
SCLK Low Pulse Width
t7
10
10
ns min
SCLK Edge to Data Valid Hold Time
t8
6
10
10
ns min
SCLK Falling Edge to SDATA 3-State Enabled
45
45
ns max
SCLK Falling Edge to SDATA 3-State Enabled
tPOWER-UP
7
T B D
T B D
µs max
Power-Up Time from Full Power-Down
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of 1.6 Volts.
2See Figure 1 and the “Serial Interface” section.
3Common Mode Voltage.
4Mark/Space ratio for the SCLK input is 40/60 to 60/40.
5Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
DD = 5 V and time for
an output to cross 0.4 V or 2.0 V for VDD = 3 V.
6t
8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured num-
ber is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the
timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
7 See ‘Power-up Time’ Section.
Specifications subject to change without notice.
Parameter
A Version
1
B Version
1
Units
Test Conditions/Comments
POWER REQUIREMENTS
V DD
3/5
3/5
Vmin/max
Range: 3 V ± 10%; 5 V ± 5%
I DD
8,10
Normal Mode(Static)
1
1
mA typ
VDD =3 V/5 V. SCLK On or Off
Normal Mode (Operational)
2.6
2.6
mA max
VDD = 5 V. fSAMPLE=1MSPS
2
2
mA max
VDD = 3 V. fSAMPLE=833kSPS
Full Power-Down Mode
1
1
µA max
SCLK On or Off
Power Dissipation
Normal Mode (Operational)
13
13
mW max
VDD =5 V. fSAMPLE=1MSPS
6
6
mW max
VDD =3 V. fSAMPLE=833kSPS
Full Power-Down
5
5
µW max
VDD =5 V. SCLK On or Off
3
3
µW max
VDD =3 V. SCLK On or Off
AD7450 - TIMING SPECIFICATIONS
1,2
( VDD = 2.7V to 3.3V, fSCLK = 15MHz, fS = 833kHz, VREF = 1.25 V;
VDD = 4.75V to 5.25V, fSCLK = 18MHz, fS = 1MHz, VREF = 2.5 V;
VCM
3 = V
REF; TA = TMIN to TMAX, unless otherwise noted.)
AD7450
NOTES
1Temperature ranges as follows: A, B Versions: –40°C to +85°C.
2See ‘Terminology’ section.
3Common Mode Voltage.
The input signal can be centered on any choice of dc Common Mode Voltage as long as this value is in the range
specified in Figure 8.
4Because the input span of V
IN+ and VIN- are both VREF, and they are 180° out of phase, the differential voltage is 2 x VREF.
5The reference is functional from 100mV and for 5V supplies it can range up to TBDV (see ‘Reference Section’).
6The reference is functional from 100mV and for 3V supplies it can range up to 2.2V (see ‘Reference Section’).
7Sample tested @ +25°C to ensure compliance.
8See POWER VERSUS THROUGHPUT RATE section.
8T
CONVERT +
TQUIET (See ‘Serial Interface Section’)
10Measured with a midscale DC input.
Specifications subject to change without notice.


Similar Part No. - AD7450ARM

ManufacturerPart #DatasheetDescription
logo
Analog Devices
AD7450ARMZ AD-AD7450ARMZ Datasheet
435Kb / 22P
   Differential Input, 1 MSPS 12-Bit ADC in SOIC-8 and SO-8
REV. A
AD7450ARMZ AD-AD7450ARMZ Datasheet
435Kb / 22P
   Differential Input, 1 MSPS ADC in SOIC-8 and SO-8
REV. A
AD7450ARMZ AD-AD7450ARMZ Datasheet
500Kb / 23P
   Differential Input, 1 MSPS 12-Bit ADC
AD7450ARMZ-REEL7 AD-AD7450ARMZ-REEL7 Datasheet
435Kb / 22P
   Differential Input, 1 MSPS 12-Bit ADC in SOIC-8 and SO-8
REV. A
AD7450ARMZ-REEL7 AD-AD7450ARMZ-REEL7 Datasheet
435Kb / 22P
   Differential Input, 1 MSPS ADC in SOIC-8 and SO-8
REV. A
More results

Similar Description - AD7450ARM

ManufacturerPart #DatasheetDescription
logo
Analog Devices
AD7450 AD-AD7450_15 Datasheet
435Kb / 22P
   Differential Input, 1 MSPS 12-Bit ADC in SOIC-8 and SO-8
REV. A
AD7450BRZ AD-AD7450BRZ Datasheet
435Kb / 22P
   Differential Input, 1 MSPS 12-Bit ADC in SOIC-8 and SO-8
REV. A
AD7450BRM-REEL AD-AD7450BRM-REEL Datasheet
435Kb / 22P
   Differential Input, 1 MSPS ADC in SOIC-8 and SO-8
REV. A
AD7298 AD-AD7298 Datasheet
1Mb / 18P
   8-Channel, 1MSPS, 12-Bit SAR ADC with Temperature Sensor
Rev. PrA
AD7451 AD-AD7451 Datasheet
208Kb / 15P
   Pseudo Differential, 1MSPS, 12- & 10-Bit ADCs in 8-lead SOT-23
REV. PrC 24/05/02
logo
Linear Technology
LTC1198 LINER-LTC1198_15 Datasheet
905Kb / 28P
   8-Bit, SO-8, 1Msps ADCs with Auto-Shutdown Options
logo
Analog Devices
AD7452 AD-AD7452_15 Datasheet
734Kb / 29P
   Differential Input, 555 kSPS 12-Bit ADC in an 8-Lead SOT-23
REV. B
logo
Linear Technology
LTC1196 LINER-LTC1196_15 Datasheet
905Kb / 28P
   8-Bit, SO-8, 1Msps ADCs with Auto-Shutdown Options
logo
Analog Devices
AD7452 AD-AD7452_17 Datasheet
639Kb / 25P
   Differential Input, 555 kSPS 12-Bit ADC in an 8-Lead SOT-23
AD7452 AD-AD7452 Datasheet
659Kb / 28P
   Differential Input, 555 kSPS 12-Bit ADC in an 8-Lead SOT-23
REV. B
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com