PCA9555APW datasheet(8/39 Pages) NXP

Part #	PCA9555APW

Description	Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up

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PCA9555A

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Product data sheet

Rev. 1 — 11 September 2012

8 of 39

NXP Semiconductors

PCA9555A

Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up

6.3 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a

high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the

Output port register. In this case, there are low-impedance paths between the I/O pin and

either VDD or VSS. The external voltage applied to this I/O pin should not exceed the

recommended levels for proper operation.

At power-on reset, all registers return to default values.

Fig 6.

Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)

VDD

P0_0 to P0_7

P1_0 to P1_7

output port

register data

configuration

register

DQ

CK

Q

data from

shift register

write configuration

pulse

output port

register

DQ

CK

write pulse

polarity inversion

register

DQ

CK

data from

shift register

write polarity

pulse

input port

register

DQ

CK

read pulse

input port

register data

polarity inversion

register data

002aah328

FF

data from

shift register

FF

Q1

Q2

VSS

to INT

100 kΩ

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