REV. 0

–3–

AD7664

Parameter

Conditions

Min

Typ

Max

Unit

POWER SUPPLIES (Continued)

Power Dissipation

7

570 kSPS Throughput

4

97

115

mW

100 SPS Througput

6

21

µW

In Power-Down Mode

7

7

µW

TEMPERATURE RANGE

8

Specified Performance

–40

+85

°C

NOTES

µV.

Specifications subject to change without notice.

TIMING SPECIFICATIONS

Symbol

Min

Typ

Max

Unit

Refer to Figures 11 and 12

Convert Pulsewidth

5ns

Time Between Conversions

1.75/2/2.25

Note 1

µs

(Wrap Mode/Normal Mode/Impulse Mode)

CNVST LOW to BUSY HIGH Delay

25

ns

BUSY HIGH All Modes Except in

1.5/1.75/2

µs

Master Serial Read After Convert Mode

(Warp Mode/Normal Mode/Impulse Mode)

Aperture Delay

2ns

End of Conversion to BUSY LOW Delay

10

ns

Conversion Time

1.5/1.75/2

µs

(Warp Mode/Normal Mode/Impulse Mode)

Acquisition Time

250

ns

RESET Pulsewidth

10

ns

Refer to Figures 13, 14, and 15 (Parallel Interface Modes)

CNVST LOW to DATA Valid Delay

1.5/1.75/2

µs

(Warp Mode/Normal Mode/Impulse Mode)

DATA Valid to BUSY LOW Delay

45

ns

Bus Access Request to DATA Valid

40

ns

Bus Relinquish Time

550

ns

Refer to Figures 16 and 17 (Master Serial Interface Modes)

2

CS LOW to SYNC Valid Delay

10

ns

10

ns

CS LOW to SDOUT Delay

10

ns

CNVST LOW to SYNC Delay

25/275/525

ns

(Warp Mode/Normal Mode/Impulse Mode)

SYNC Asserted to SCLK First Edge Delay

4ns

Internal SCLK Period

40

75

ns

Internal SCLK HIGH (INVSCLK Low)

3

30

ns

Internal SCLK LOW (INVSCLK Low)

3

9.5

ns

SDOUT Valid Setup Time

4.5

ns

SDOUT Valid Hold Time

3ns

SCLK Last Edge to SYNC Delay

3

CS HIGH to SYNC HI-Z

10

ns

CS HIGH to Internal SCLK HI-Z

10

ns

CS HIGH to SDOUT HI-Z

10

ns

BUSY HIGH in Master Serial Read After Convert

2.75/3/3.25

µs

(Warp Mode/Normal Mode/Impulse Mode)

CNVST LOW to SYNC Asserted Delay

1/1.25/1.5

µs

(Warp Mode/Normal Mode/Impulse Mode)

SYNC Deasserted to BUSY LOW Delay

50

ns

(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)