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AD7651 Datasheet(PDF) 6 Page - Analog Devices

Part # AD7651
Description  16-Bit 1 MSPS SAR Unipolar ADC with Ref
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7651 Datasheet(HTML) 6 Page - Analog Devices

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REV. PrA
PRELIMINARY TECHNICAL DATA
–6–
AD7667
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Type
Description
1
AGND
P
Analog Power Ground Pin
2
AVDD
P
Input Analog Power Pins. Nominally 5 V.
3, 40–42,
NC
No Connect
44
4
BYTESWAP
DI
Parallel Mode Selection (8/16 bit). When LOW, the LSB is output on D[7:0] and the
MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB
is output on D[7:0].
5
OB/
2C
DI
Straight Binary/Binary Two’s Complement. When OB/
2C is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a two’s complement output
from its internal shift register.
6
WARP
DI
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode,
the maximum throughput is achievable, and a minimum conversion rate must be applied
in order to guarantee full specified accuracy. When LOW, full accuracy is maintained
independent of the minimum conversion rate.
7
IMPULSE
DI
Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode.
In this mode, the power dissipation is approximately proportional to the sampling rate.
8
SER/
PAR
DI
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
serial interface mode is selected and some bits of the DATA bus are used as a serial port.
9,10
DATA[0:1]
DI
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/
PAR is HIGH, these
outputs are in high impedance.
11,12
DATA[2:3]or
DI/O
When SER/
PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port
DIVSCLK[0:1]
Data Output Bus. When SER/
PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is
LOW, which is serial master read after convert, these inputs, part of the serial port, are
used to slow down if desired the internal serial clock which clocks the data output. In
other serial moes, these pins are not used
13
DATA[4]
DI/O
When SER/
PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output
Bus.
or EXT/
INT
When SER/
PAR is HIGH, this input, part of the serial port, is used as a digital select input
for choosing the internal or an external data clock. With EXT/
INT tied LOW, the internal
clock is selected on SCLK output. With EXT/
INT set to a logic HIGH, output data is syn
chronized to an external clock signal connected to the SCLK input.
14
DATA[5]
DI/O
When SER/
PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output
Bus.
or INVSYNC
When SER/
PAR is HIGH, this input, part of the serial port, is used to select the active
PIN CONFIGURATION
48-Lead LQFP
(ST-48)
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
AGND
AVDD
NC
BYTESWAP
OB/2C
WARP
IMPULSE
NC = NO CONNECT
SER/PAR
D0
D1
D2/SCLK0
BUSY
D15
D14
D13
AD7667
D3/SCLK1
D12


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