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AD7660 Datasheet(PDF) 3 Page - Analog Devices

Part # AD7660
Description  16-Bit 1 MSPS SAR Unipolar ADC with Ref
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

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REV. Pr
A
PRELIMINARY TECHNICAL DATA
–3–
AD7667
Parameter
Conditions
Min
Typ
Max
Unit
TIMING SPECIFICATIONS
Symbol
Min
Typ
Max
Unit
REFER TO FIGURES 11 AND 12
Convert Pulsewidth
t1
5ns
Time Between Conversions
t2
1/1.25/1.5
Note 1
µs
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay
t3
30
ns
BUSY HIGH All Modes Except in
t4
0.75/1/1.25
µs
Master Serial Read After Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
t5
2ns
End of Conversion to BUSY LOW Delay
t6
10
ns
Conversion Time
t7
0.75/1/1.25
µs
(Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
t8
250
ns
RESET Pulsewidth
t9
10
ns
REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
t10
0.75/1/1.25
µs
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
t11
45
ns
Bus Access Request to DATA Valid
t12
40
ns
Bus Relinquish Time
t13
515
ns
REFER TO FIGURES 16 AND 17 (Master Serial Interface Modes)2
CS LOW to SYNC Valid Delay
t14
10
ns
CS LOW to Internal SCLK Valid Delay2
t15
10
ns
CS LOW to SDOUT Delay
t16
10
ns
CNVST LOW to SYNC Delay
t17
25/275/525
ns
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
t18
3ns
Internal SCLK Period
3
t19
25
40
ns
Internal SCLK HIGH
3
t20
12
ns
Internal SCLK LOW3
t21
7ns
SDOUT Valid Setup Time
3
t22
4ns
SDOUT Valid Hold Time
3
t23
2ns
SCLK Last Edge to SYNC Delay3
t24
3
CS HIGH to SYNC HI-Z
t25
10
ns
CS HIGH to Internal SCLK HI-Z
t26
10
ns
CS HIGH to SDOUT HI-Z
t27
10
ns
BUSY HIGH in Master Serial Read after Convert
3
t28
See Table I
µs
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to SYNC Asserted Delay
t29
0.75/1/1.25
µs
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
t30
25
ns
(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Operating Current
4
1 MSPS Throughput
AVDD
5
TBD
mA
DVDD
5
TBD
mA
OVDD
5
TBD
µA
Power Dissipation
5 without REF
1 MSPS Throughput
112
mW
100 SPS Throughput
6
15
µW
In Power-Down Mode
7
TBD
µW
Power Dissipation
5 with REF
1 MSPS Throughput
122
mW
100 SPS Throughput
6
10.015
mW
In Power-Down Mode
7
TBD
µW
TEMPERATURE RANGE
8
Specified Performance
TMIN to TMAX
–40
+85
°C
NOTES
1LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15 µV.
2See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
4In warp mode.
5Tested in parallel reading mode using external reference.
6In impulse mode with external REF.
7With all digital inputs forced to DVDD or DGND respectively.
8Contact factory for extended temperature range.
9The max should be the minimum of 5.25V and DVDD+0.3 V.
Specifications subject to change without notice.


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