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AD7652 Datasheet(PDF) 4 Page - Analog Devices |
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AD7652 Datasheet(HTML) 4 Page - Analog Devices |
4 / 23 page REV. PrA PRELIMINARY TECHNICAL DATA –4– AD7667 Table I. Serial clock timings in Master Read after Convert DIVSCLK[1] 0011 unit DIVSCLK[0] 0101 SYNC to SCLK First Edge Delay Minimum t18 3 171717ns Internal SCLK Period minimum t19 25 50 100 200 ns Internal SCLK Period typical t19 40 70 140 280 ns Internal SCLK HIGH Minimum t20 12 22 50 100 ns Internal SCLK LOW Minimum t21 7 214999ns SDOUT Valid Setup Time Minimum t22 4 181818ns SDOUT Valid Hold Time Minimum t23 2 4 3089ns SCLK Last Edge to SYNC Delay Minimum t24 3 60 140 300 ns Busy High Width Maximum (Warp) t24 1.5 2 3 5.25 µs Busy High Width Maximum (Normal) t24 1.75 2.25 3.25 5.55 µs Busy High Width Maximum (Impulse) t24 2 2.5 3.5 5.75 µs REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes) 2 External SCLK Setup Time t31 5ns External SCLK Active Edge to SDOUT Delay t32 318 ns SDIN Setup Time t33 5ns SDIN Hold Time t34 5ns External SCLK Period t35 25 ns External SCLK HIGH t36 10 ns External SCLK LOW t37 10 ns NOTES 1In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum. 3In serial master read during convert mode. See Table I for serial master read after convert mode. Specifications subject to change without notice. Symbol Min Typ Max Unit |
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