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AD7707 Datasheet(PDF) 5 Page - Analog Devices |
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AD7707 Datasheet(HTML) 5 Page - Analog Devices |
5 / 40 page REV. A AD7707 –5– TIMING CHARACTERISTICS 1, 2 Limit at TMIN, TMAX Parameter (B Version) Units Conditions/Comments fCLKIN 3, 4 400 kHz min Master Clock Frequency: Crystal Oscillator or Externally Supplied for 5 MHz max Specified Performance tCLKIN LO 0.4 × t CLKIN ns min Master Clock Input Low Time. tCLKIN = 1/fCLKIN tCLKIN HI 0.4 × t CLKIN ns min Master Clock Input High Time t1 500 × t CLKIN ns nom DRDY High Time t2 100 ns min RESET Pulsewidth Read Operation t3 0 ns min DRDY to CS Setup Time t4 120 ns min CS Falling Edge to SCLK Rising Edge Setup Time t5 5 0 ns min SCLK Falling Edge to Data Valid Delay 80 ns max DVDD = +5 V 100 ns max DVDD = +3.0 V t6 100 ns min SCLK High Pulsewidth t7 100 ns min SCLK Low Pulsewidth t8 0 ns min CS Rising Edge to SCLK Rising Edge Hold Time t9 6 10 ns min Bus Relinquish Time after SCLK Rising Edge 60 ns max DVDD = +5 V 100 ns max DVDD = +3.0 V t10 100 ns max SCLK Falling Edge to DRDY High 7 Write Operation t11 120 ns min CS Falling Edge to SCLK Rising Edge Setup Time t12 30 ns min Data Valid to SCLK Rising Edge Setup Time t13 20 ns min Data Valid to SCLK Rising Edge Hold Time t14 100 ns min SCLK High Pulsewidth t15 100 ns min SCLK Low Pulsewidth t16 0 ns min CS Rising Edge to SCLK Rising Edge Hold Time NOTES 1Sample tested at +25 °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV DD) and timed from a voltage level of 1.6 V. 2See Figures 16 and 17. 3f CLKIN Duty Cycle range is 45% to 55%. f CLKIN must be supplied whenever the AD7707 is not in Standby mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4The AD7707 is production tested with f CLKIN at 2.4576 MHz (1 MHz for some IDD tests). It is guaranteed by characterization to operate at 400 kHz. 5These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V OL or VOH limits. 6These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. 7 DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high, although care should be taken that subsequent reads do not occur close to the next output update. TO OUTPUT PIN 50pF ISINK (800 A AT VDD = +5V 100 A AT VDD = +3V) +1.6V ISOURCE (200 A AT VDD = +5V 100 A AT VDD = +3V) Figure 1. Load Circuit for Access Time and Bus Relinquish Time (AVDD = DVDD = +2.7 V TO +5.25 V, AGND = DGND = 0 V; fCLKIN = 2.4576 MHz; Input Logic = 0, Logic 1 = DVDD unless otherwise noted.) |
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