Electronic Components Datasheet Search |
|
AD7713 Datasheet(PDF) 5 Page - Analog Devices |
|
AD7713 Datasheet(HTML) 5 Page - Analog Devices |
5 / 28 page 2 –5– REV. C AD7713 Limit at TMIN, TMAX Parameter (A, S Versions) Units Conditions/Comments External-Clocking Mode fSCLK fCLK IN/5 MHz max Serial Clock Input Frequency t20 0 ns min DRDY to RFS Setup Time t21 0 ns min DRDY to RFS Hold Time t22 2 × t CLK IN ns min A0 to RFS Setup Time t23 0 ns min A0 to RFS Hold Time t24 6 4 × t CLK IN ns max Data Access Time (RFS Low to Data Valid) t25 6 10 ns min SCLK Falling Edge to Data Valid Delay 2 × t CLK IN + 20 ns max t26 2 × t CLK IN ns min SCLK High Pulse Width t27 2 × t CLK IN ns min SCLK Low Pulse Width t28 tCLK IN + 10 ns max SCLK Falling Edge to DRDY High t29 7 10 ns min SCLK to Data Valid Hold Time tCLK IN + 10 ns max t30 10 ns min RFS /TFS to SCLK Falling Edge Hold Time t31 7 5 × t CLK IN/2 + 50 ns max RFS to Data Valid Hold Time t32 0 ns min A0 to TFS Setup Time t33 0 ns min A0 to TFS Hold Time t34 4 × t CLK IN ns min SCLK Falling Edge to TFS Hold Time t35 2 × t CLK IN – SCLK High ns min Data Valid to SCLK Setup Time t36 30 ns min Data Valid to SCLK Hold Time NOTES 1Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2See Figures 10 to 13. 3CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7713 is not in STANDBY mode. If no clock is present in this case, the device can draw higher current than specified and possibly become uncalibrated. 4The AD7713 is production tested with f CLK IN at 2 MHz. It is guaranteed by characterization to operate at 400 kHz. 5Specified using 10% and 90% points on waveform of interest. 6These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 7These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. TO OUTPUT PIN +2.1V 1.6mA 200µA 100pF Figure 1. Load Circuit for Access Time and Bus Relinquish Time |
Similar Part No. - AD7713 |
|
Similar Description - AD7713 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |