REV. F

–10–

AD7711

PGA Gain

G2

Gl

G0

Gain

0

0

0

1

(Default Condition After the Internal Power-On Reset)

001

2

010

4

011

8

100

16

101

32

110

64

111

128

Channel Selection

CH

Channel

0

AIN1

(Default Condition After the Internal Power-On Reset)

1

AIN2

Power-Down

PD

0

Normal Operation

(Default Condition After the Internal Power-On Reset)

1

Power-Down

Word Length

WL

Output Word Length

0

16-bit

(Default Condition After Internal Power-On Reset)

1

24-bit

RTD Excitation Current

IO

0

Off

(Default Condition After Internal Power-On Reset)

1On

Burnout Current

BO

0

Off

(Default Condition After Internal Power-On Reset)

1On

Bipolar/Unipolar Selection (Both Inputs)

B/U

0

Bipolar

(Default Condition After Internal Power-On Reset)

1

Unipolar

Filter Selection (FS11–FS0)

The on-chip digital filter provides a Sinc

the filter cutoff frequency, the position of the first notch of the filter and the data rate for the part. In association with the gain selec-

tion, it also determines the output noise (and hence the effective resolution) of the device.

10 MHz, this results in a first notch frequency range from 9.76 Hz to 1.028 kHz. To ensure correct operation of the AD7711, the

value of the code loaded to these bits must be within this range. Failure to do this will result in unspecified operation of the device.

Changing the filter notch frequency, as well as the selected gain, impacts resolution. Tables I and II and Figure 2 show the effect of

the filter notch frequency and gain on the effective resolution of the AD7711. The output data rate (or effective conversion time) for

the device is equal to the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected at

50 Hz, then a new word is available at a 50 Hz rate or every 20 ms. If the first notch is at 1 kHz, a new word is available every 1 ms.

The settling time of the filter to a full-scale step input change is worst case 4

× 1/(output data rate). This settling time is to 100% of

the final value. For example, with the first filter notch at 50 Hz, the settling time of the filter to a full-scale step input change is

80 ms max. If the first notch is at 1 kHz, the settling time of the filter to a full-scale input step is 4 ms max. This settling time can be

reduced to 3

× 1/(output data rate) by synchronizing the step input change to a reset of the digital filter. In other words, if the step

input takes place with

SYNC low, the settling time will be 3

× 1/(output data rate). If a change of channels takes place, the settling

time is 3

× 1/(output data rate) regardless of the SYNC input.

The –3 dB frequency is determined by the programmed first notch frequency according to the relationship: filter –3 dB frequency

= 0.262

× first notch frequency.