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AD8011AR-REEL Datasheet(PDF) 11 Page - Analog Devices |
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AD8011AR-REEL Datasheet(HTML) 11 Page - Analog Devices |
11 / 16 page AD8011 REV. B –11– 1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09 400 370 340 310 280 220 190 FREQUENCY – Hz 250 20 0 –20 –40 –120 160 130 100 –140 –160 –180 –60 –80 –100 SERIES 1 IMPEDANCE ZI(s) SERIES 2 PHASE Figure 32. Open-Loop Inverting Input Impedance ZI (s) goes positive real and approaches 1/2 gmf as ω approaches (gmc × R1 – 1)/τ1. This results in the input resistance for the AV (s) complex term being 1/2 gmf; the parallel thermal emitter resistances of Q3/Q4. Using the computed CLBW from AV (s) above and the nominal design values for the other parameters, results in a closed loop 3 dB BW equal to the open loop corner frequency (1/2 πτ1) times 1/[G/(2 g mf × T O) + RF/TO]. For a fixed RF, the 3 dB BW is controlled by the RF/TO term for low gains and G/(2 gmf × TO) for high gains. For example, using nominal design parameters and R1 = 1 k Ω (which results in a nominal TO of 1.2 M Ω, the computed BW is 80 MHz for G = 0 (inverting I-V mode with RN removed) and 40 MHz for G = +10/–9. DRIVING CAPACITIVE LOADS The AD8011 was designed primarily to drive nonreactive loads. If driving loads with a capacitive component is desired, best settling response is obtained by the addition of a small series resistance as shown in Figure 33. The accompanying graph shows the optimum value for RSERIES vs. capacitive load. It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of RSERIES and CL. 1k RL 1k CL RSERIES 1k AD8011 Figure 33. Driving Capacitive Load where R1 is the input resistance to A2/A2B, and τ1 (equal to CD × R1 × A2) is the open loop dominate time constant. and TO (s) = |A2| ×R1 2 s τ1+1 1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09 FREQUENCY – Hz 140 120 100 80 60 20 0 40 0 –40 –80 –120 –160 –200 –240 –280 PHASE GAIN TO(s) Figure 31. Open-Loop Transimpedance Gain Note that the ac open-loop plots in Figures 31, 32 and 33 are based on the full Spice AD8011 simulations and do not include external parasitics (see below). Nevertheless, these ac loop equa- tions still provide a good approximation to simulated and actual performance up to the CLBW of the amplifier. Typically gmc × R1 is –4, resulting in AO(s) having a right half plane pole. In the time domain (inverse Laplace of AO) it appears as unstable, causing VO to exponentially rail out of its linear region. When the loop is closed however, the BW is greatly extended and the transimpedance gain, TO (s) “overrides” and directly controls the amplifiers stability behavior due to ZI approaching 1/2 gmf for s>>1/ τ1. See Figure 32. This can be seen by the ZI (s) and AV (s) noninverting transfer equations below. Z I (s) = (1 – g mc × R1) S τ1 1 – g mc × R1 + 1 2 × g mf ( S τ1+ 1) AV(s) = G 1 + G AO + RF TO S τ1 G 2 gmf TO + RF TO + 1 |
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