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AD8313ARM-REEL7 Datasheet(PDF) 9 Page - Analog Devices |
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AD8313ARM-REEL7 Datasheet(HTML) 9 Page - Analog Devices |
9 / 16 page AD8313 –9– REV. B With Pins 7 and 8 disconnected (controller mode), the output may be stated as VOUT v VS when VSLOPE (PIN + 100) > VSET VOUT v 0 when VSLOPE (PIN + 100) < VSET when the input is stated in terms of the power of a sinusoidal signal across a net termination impedance of 50 Ω. The transi- tion zone between high and low states is very narrow, since the output stage behaves essentially as a fast integrator. The above equations may be restated as VOUT v VS when VSLOPE log (VIN/2.2 µV) > V SET VOUT v 0 when VSLOPE log (VIN/2.2 µV) < V SET A further use of the separate VOUT and VSET pins is in raising the load-driving current capability by the inclusion of an ex- ternal NPN emitter follower. More complete information about usage in these various modes is provided in the Applications section. INTERFACES This section describes the signal and control interfaces and their behavior. On-chip resistances and capacitances exhibit varia- tions of up to ±20%. These resistances are sometimes tempera- ture dependent and the capacitances may be voltage dependent. Power-Down Interface, PWDN The power-down threshold is accurately centered at the midpoint of the supply as shown in Figure 22. If Pin 5 is left unconnected or tied to the supply voltage (recommended) the bias enable cur- rent is shut off, and the current drawn from the supply is pre- dominately through a nominal 300 k Ω chain (20 µA at 3 V). When grounded, the bias system is turned on. The threshold level is accurately at VPOS/2. The input bias current at the PWDN pin when operating in the device “ON” state is approximately 5 µA for V POS = 3 V. 5 PWDN VPOS 75k 6 COMM 150k 50k 150k TO BIAS ENABLE 4 Figure 22. Power-Down Threshold Circuitry Signal Inputs, INHI, INLO The simplest low frequency ac model for this interface consists of just a 900 Ω resistance R IN in shunt with a 1.1 pF input ca- pacitance, CIN connected across INHI and INLO. Figure 23 shows these distributed in the context of a more complete sche- matic. The input bias voltage shown is for the enabled chip; when disabled, it will rise by a few hundred millivolts. If the input is coupled via capacitors, this change may cause a low- level signal transient to be introduced, having a time-constant formed by these capacitors and RIN. For this reason, large- valued coupling capacitors should be well matched; this is not necessary when using the small capacitors found in many im- pedance transforming networks used at high frequencies. 1.25k COMM VPOS INHI INLO VPOS 0.5pF 0.5pF 0.7pF 2.5k 2.5k ~0.75V (1ST DETECTOR) 250 ~1.4mA 125 125 1.25k 1.24V GAIN BIAS TO 2ND STAGE TO STAGES 1 THRU 4 1 2 3 4 Figure 23. Input Interface Simplified Schematic For high frequency use, Figure 24 shows the input impedance plotted on a Smith chart. This measured result of a typical de- vice includes a 191 mil 50 Ω trace and a 680 pF capacitor to ground from the INLO pin. 1.1pF 900 1.9GHz Frequency 100MHz 900MHz 1.9GHz 2.5GHz R 650 55 22 23 +j X –j 400 –j 135 –j 65 –j 43 AD8313 MEASURED 2.5GHz 900MHz 100MHz Figure 24. Typical Input Impedance Logarithmic/Error Output, VOUT The rail-to-rail output interface is shown in Figure 25. VOUT can run from within about 50 mV of ground, to within about 100 mV of the supply voltage, and is short-circuit safe to either supply. However, the sourcing load current ISOURCE is limited by that provided by the PNP transistor, to typically 400 µA. Larger load currents can be provided by adding an external NPN tran- sistor (see Applications). The dc open-loop gain of this amplifier is high, and it may be regarded essentially as an integrator hav- ing a capacitance of 2 pF (CINT) driven by the current-mode signals generated by the summed outputs of the nine detector stages, which is scaled approximately 4.0 µA/dB. COMM gm STAGE CINT LP LM 10mA MAX VOUT CL BIAS ISOURCE 400 A VPOS FROM SET-POINT SUMMED DETECTOR OUTPUTS 6 8 1 Figure 25. Output Interface Circuitry Thus, for a midscale RF input of about 3 mV, which is some 40 dB above the minimum detector output, this current is 160 µA and the output changes by 8 V/µs. When VOUT is connected to VSET, the rise and fall times are approximately 40 ns (for RL ≥ 10 kΩ). The nominal slew rate is ± 2.5 V/µs. The HF compensation technique results in stable operation with a large capacitive load, CL, though the positive-going slew rate will then be limited by ISOURCE/CL to 1 V/µs for CL = 400 pF. |
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