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AD8600 Datasheet(PDF) 4 Page - Analog Devices |
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AD8600 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 16 page  REV. 0 –4– AD8600 ELECTRICAL CHARACTERISTICS Parameter Symbol Condition Min Typ Max Units INTERFACE TIMING 1, 2 Clock (EN) Frequency fCLK Data Loading 12.5 MHz Clock (EN) High Pulse Width tCH 40 ns Clock (EN) LowPulse Width tCL 40 ns Data Setup Time tDS 40 ns Data Hold Time tDH 10 ns Address Setup Time tAS 0ns Address Hold Time tAH 0ns Valid Address to Data Valid tAD 160 ns Load Enable Setup Time tLS 0ns Load Enable Hold Time tLH 0ns Read/Write to Clock (EN)tRWC 30 ns Read/Write to DataBus Hi-Z tRWZ 120 ns Read/Write to DataBus Active tRWD 120 ns Clock (EN) to Read/Write tTWH 0ns Clock (EN) to Chip Select tTCH 0ns Chip Select to Clock (EN)tCSC 30 ns Chip Select to Data Valid tCSD 120 ns Chip Select to DataBus Hi-Z tCSZ 150 ns Reset Pulse Width tRS 25 ns NOTES 1Guaranteed by design not subject to production test. 2All logic input signals have maximum rise and fall times of 2 ns. Specifications subject to change without notice. Figure 3. Readback Timing Figure 2. Write Timing (@ VDD1 = VDD2 = VCC = +5 V ± 5%, V EE = –5 V, VREF = +3.500 V, – 40 °C ≤ T A ≤ +85°C, unless otherwise noted) tRWZ tDH tTWH HIGH-Z tAS tAH tCH tCL tTCH R/W DATA ADDR EN CS tCSC tRWC tDS Figure 4. Write to DAC Register & Voltage Output Settling Timing (CS= High, Prevents Input Register Changes) tLS tLH tS1 tRS OUT tS1 EN RS LD tRWD HIGH -Z tAD tCSZ tCSD R/W DATA ADDR EN CS |
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