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AD9244BST-65 Datasheet(PDF) 7 Page - Analog Devices |
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AD9244BST-65 Datasheet(HTML) 7 Page - Analog Devices |
7 / 36 page REV. A AD9244 –7– PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 AGND AGND AVDD AVDD AGND CLK– CLK+ NIC OEB D0 (LSB) D1 D2 D11 D12 D13 (MSB) OTR DRVDD DGND AVDD AGND AGND AVDD DFS SENSE AD9244 TOP VIEW (NOT TO SCALE) PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1, 2, 5, 32, 33 AGND Analog Ground. 3, 4, 31, 34 AVDD Analog Supply Voltage. 6, 7 CLK–, CLK+ Differential Clock Inputs. 8, 44 NIC No Internal Connection. 9 OEB Digital Output Enable (Active Low). 10 D0 (LSB) Least Significant Bit, Digital Output. 11–13, 16–21, D1–D3, D4–D9, Digital Outputs. 24–26 D10–D12 14, 22, 30 DGND Digital Ground. 15, 23, 29 DRVDD Digital Supply Voltage. 27 D13 (MSB) Most Significant Bit, Digital Output. 28 OTR Out-of-Range Indicator (Logic 1 indicates OTR). 35 DFS Data Format Select. Connect to AGND for straight binary, AVDD for twos complement. 36 SENSE Internal Reference Control. 37 VREF Internal Reference. 38 REFGND Reference Ground. 39–42 REFB, REFT Internal Reference Decoupling. 43 DCS 50% Duty Cycle Stabilizer. Connect to AVDD to activate 50% duty cycle stabilizer, AGND for external control of both clock edges. 45 CML Common-Mode Reference (0.5 × AVDD). 46, 47 VIN+, VIN– Differential Analog Inputs. 48 VR Internal Bias Decoupling. |
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