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AD9430 Datasheet(PDF) 9 Page - Analog Devices |
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AD9430 Datasheet(HTML) 9 Page - Analog Devices |
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9 / 20 page  PRELIMINARY TECHNICAL DATA AD9430 REV. PrG 4/01/2002 -9- PIN FUNCTION DESCRIPTIONS (LVDS mode ) LVDS Mode Pin Number Name Function in LVDS Mode 2,42,43,44,45,46 DNC Do not connect 1 S5 Full Scale Adjust pin : ‘1’ sets FS = .766 Vpp differential, ‘0’ sets FS = 1.533 Vpp differential 3 S4 Interlaced or parallel output mode. (only in Dual Port mode operation) HIGH = data arrives in channel A at falling edge of clock and data arrives in channelA at rising edge of clock. LOW = data arrives in channels A and B at rising edge of clock. 5 S2 Output Mode select. Low = Dual Port, CMOS; High = LVDS 6 S1 Data format select. Low = Binary, High = Two’s compliment 7 LVDSBIAS Sets LVDS Output Current = 3.5mA (Place 3.7K RSET resistor from LVDSBIAS to ground) 8,14,15,18,19,24,27,28,29,34, 39,40,88,89,90,94,95,98,99 AVDD 3.3V analog supply. (3.0V to 3.6V) 4,9,12,13,16,17,20,23,25,26,3 0,31,35,38,41,86,87,91,92,93, 96,97,100 AGND Analog Ground 10 SENSE Control Pin for Reference , Full Scale 11 VREF 1.235 Reference I/O - function dependent on REFSENSE 21 VIN+ Analog input – true. 22 VIN- Analog input – compliment. 32 DS+ Data sync (input) – Not used in LVDS mode.Tie LOW . 33 DS- Data sync (input) – compliment. Not used in LVDS mode.Tie HIGH. 36 ENC+ Clock input – true. (LVPECL levels) 37 ENC- Clock input – compliment. (LVPECL levels) 47,54,62,75,83 DrVDD 3.3V digital output supply. 48,53,61,67,74,82 DrGND Digital ground. 49 D0_C D0 complement output bit (LSB) (LVDS Levels) 50 D0_T D0 true output bit (LSB) (LVDS Levels) 51 D1_C D1 complement output bit (LVDS Levels) 52 D1_T D1 true output bit (LVDS Levels) 55 D2_C D2 complement output bit (LVDS Levels) 56 D2_T D2 true output bit (LVDS Levels) 57 D3_C D3 complement output bit (LVDS Levels) 58 D3_T D3 true output bit (LVDS Levels) 59 D4_C D4 complement output bit (LVDS Levels) 60 D4_T D4 true output bit (LVDS Levels) 63 DCO- Data Clock output – compliment. (LVDS Levels) 64 DCO+ Data Clock output – true. (LVDS Levels) 65 D5_C D5 complement output bit (LVDS Levels) 66 D5_T D5 true output bit (LVDS Levels) 68 D6_C D6 complement output bit (LVDS Levels) 69 D6_T D6 true output bit (LVDS Levels) 70 D7_C D7 complement output bit (LVDS Levels) 71 D7_T D7 true output bit (LVDS Levels) 72 D8_C D8 complement output bit (LVDS Levels) 73 D8_T D8 true output bit (LVDS Levels) 76 D9_C D9 complement output bit (LVDS Levels) 77 D9_T D9 true output bit (LVDS Levels) 78 D10_C D10 complement output bit (LVDS Levels) 79 D10_T D10 true output bit (LVDS Levels) 80 D11_C D11 complement output bit (LVDS Levels) MSB 81 D11_T D11 true output bit (LVDS Levels) MSB 84 OR_C Overrange complement output bit (LVDS Levels) 85 OR_T Overrange true output bit (LVDS Levels) |
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