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AD9500 Datasheet(PDF) 10 Page - Analog Devices |
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AD9500 Datasheet(HTML) 10 Page - Analog Devices |
10 / 11 page AD9500 –10– REV. D LAYOUT CONSIDERATIONS The AD9500 is a precision timing device, and as such high frequency design techniques must be employed to achieve the best performance. The use of a low impedance ground plane is particularly important. Ideally the ground plane should be on the component side of the layout and extend under the AD9500, to shield it from system timing signals. Sockets pose a special problem for a circuit like the AD9500 because of the additional inter-lead capacitance they create. If sockets must be used, pin sockets are generally preferred. Power supply decou- pling is also critical to a high-speed design; a 0.1 µF ceramic capacitor and a 0.01 µF mica capacitor for both power supplies should be very effective. DAC threshold stability can be improved by decoupling the OFFSET ADJUST pin to +5.0 V (note that this will lengthen the DAC settling time, tDAC) DELAY OFFSET ADJUSTMENTS As the full-scale delay is increased, a component of the mini- mum propagation delay also increases. This is caused by the additional time required by the ramp (now with a much “flatter” slope) to fall below the DAC threshold corresponding to the minimum propagation delay (tPD). One means of decreasing the minimum propagation delay (when the full-scale delay, set by RSET and CEXT is large) is to offset the internal DAC threshold toward the initial ramp levels, thus reducing the time for the internal ramp to cross the threshold once the AD9500 is triggered. Figure 11. The Offset Adjust Pin Can Be Used to Match Several AD9500s The DAC levels are offset toward the initial ramp level by in- jecting a small current into the offset adjust pin. Note, however, that the ramp start-up region is less linear than the later portions of the ramp, which is the primary reason for the built-in offset. If the minimum propagation delay is kept above 5 ns (the linear portion of the ramp), no significant degradation in linearity should result. This concept can be extended to match the actual propagation delays of several AD9500s, by injecting or sinking a small current (<2 mA) into or out of each of the OFFSET ADJUST pins. GENERAL PERFORMANCE ENHANCEMENTS High speed operation is generally more consistent if CEXT is kept small (i.e., no external capacitor) to maintain small dis- charge time constants. Integral linearity, however, benefits from larger values of CEXT by buffering small system spikes and surges. Another means of improving integral linearity is to draw a small current ( ≈200 µA) out of the OFFSET ADJUST pin with a 47 k Ω pull-down resistor. This has the effect of moving the internal DAC reference levels into a relatively more linear region of the ramp. This technique is generally only useful for small full-scale delay configurations. Its use with larger full-scale delays will extend the minimum propagation delay (tPD). A pull- up resistor to +5.0 V creates the opposite effect by reducing the minimum propagation delay (tPD) at the expense of increased reset propagation delay (tRD) and degraded linearity (see OFF- SET matching circuit). Caution should be used when applying high slew rate data at the inputs of the AD9500. For data inputs with slew rates in excess of 1 V/ns, a 100 Ω series resistor should be utilized in the data path. An external DAC can be used with the AD9500 for increased resolution and higher update rates. For the most part, a stan- dard ECL DAC, operating between +5.0 V and ground, should work with the AD9500. The output of the external DAC must be connected to the OFFSET ADJUST pin of the AD9500 with the internal DAC turned off (D0 thru D7 at logic LOW). For normal operation, the external DAC output should range from 0 mA to –2 mA (sinking). Figure 12. Operation with External DAC |
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