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AD9501JP Datasheet(PDF) 10 Page - Analog Devices |
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AD9501JP Datasheet(HTML) 10 Page - Analog Devices |
10 / 12 page AD9501 REV. A –10– Figure 8. Digital Delay Detector Figure 7. Programmable Pulse Delay Generator AD9501 #1 should be programmed so its delay is greater than the zero-set programmed delay of AD9501 #2. To accomplish this, continue to apply clock pulses and increment the digital data into AD9501 #1 until the output of the successive approxi- mation register (SAR) is 02H (00000010) or greater. At this point, the delay through AD9501 #1 is slightly longer than the delay through AD9501 #2, making it possible to use the SAR output as the zero reference point for measuring the unknown delay when it is reinserted into the circuit. This calibration procedure compensates for the setup time of the flip-flop, stray circuit delays and other nonideal characteristics which are an inherent part of any circuit. Eight cycles of the clock input are required to determine the value of the unknown delay. |
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