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AD9660 Datasheet(PDF) 9 Page - Analog Devices

Part # AD9660
Description  200 MHz Laser Diode Driver with Light Power Control
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9660 Datasheet(HTML) 9 Page - Analog Devices

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AD9660
REV. 0
–9–
Example Calculations
The example below (in addition to the one included in the sec-
tions above) should guide users in choosing RGAIN, CGAIN, the
hold capacitor values, and worst case calibration times.
System Requirements:
• Bias laser power: 4 mW Bias ± 5%
• Write laser power: 25 mW ± 0.5%
• Bias Hold Time: 1 ms
• Write Hold Time: 1 µs
Laser diode/photo diode characteristics:
• Laser efficiency 0.5 mA/mA
• Monitor current: 5 µA/mA
• From the laser power requirements and efficiency we can
estimate:
∆I
BIAS MAX = 4 mW × (5% ) /
0. 5
mW
mA


= 400.0 µA
and
∆I
WRITE MAX = 25 mW × 0. 5%
(
) /0.5 mW
mA


= 250 µA
• Choosing hold caps based on these:
C
BIAS HOLD =
18
×10
−9 ×1ms
400
µA
= 0.045 µF
and
C
WRITE HOLD =
18
×10
−9 ×1µs
250
µA
= 72 pF
• The bias loop initial calibration time for a <1% error:
5
τ = 5 × RC = 5 × 550
Ω × 0.045 µF = 123.75 µs
• Bias loop recalibration for a 1% error after 5% droop (need to
correct within 20%):
2
τ = 2 × RC = 2 × 140
Ω × 0.045 µF = 12.6 µs
• The write loop initial calibration time for <0.1% error:
7
τ = 7 × RC = 7 × 550
Ω × 72 pF = 277.2 ns
• Write loop re-calibration for a 0.1% error after 0.5% droop
(need to correct within 20%):
2
τ = RC = 2 × 140
Ω × 72 pF = 20.2 ns
• From the monitor current specification and the max power
specified:
I MONITOR MAX = 25 mW
5
µA
mW
= 125 µA
and
R
GAIN =
1.6 V
1.85
× I
MONITOR MAX
− 50 Ω= 6.9 kΩ
• C
GAIN would be chosen as 2 pF (see Table I).
Driving the Analog Inputs
The BIAS LEVEL and WRITE LEVEL inputs of the AD9660
drive the track and hold amplifiers and allow the user to adjust
the amount of output current as described above. The input
voltage range on both inputs is VREF to VREF + 1.6 V, requiring
the user to create an offset of VREF for a ground based signal.
The circuit in Figure 9 will perform the level shift and scale the
output of a DAC whose output is from ground to a positive
voltage. This solution is attractive because both the DAC and
the op amp can run off a single +5 V supply, and the op amp
doesn’t have to swing rail to rail.
DAC1
DAC2
VDAC1
VDAC2
OP291
OP291
+5V
VREF + VDAC1
= VBIAS LEVEL
R2
R1
VREF + VDAC2
= VWRITE LEVEL
R4
R3
BIAS LEVEL
VREF
WRITE LEVEL
AD9660
R1
R2
R3
R4
R3
R4
R1
R2
Figure 9. Driving the Analog Inputs


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