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AD9742 Datasheet(PDF) 9 Page - Analog Devices |
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AD9742 Datasheet(HTML) 9 Page - Analog Devices |
9 / 20 page REV. 0 AD9742 –9– FUNCTIONAL DESCRIPTION Figure 3 shows a simplified block diagram of the AD9742. The AD9742 consists of a DAC, digital control logic, and full-scale output current control. The DAC contains a PMOS current source array capable of providing up to 20 mA of full-scale current (IOUTFS). The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an MSB current source. The remaining LSBs are binary weighted fractions of the middle bits current sources. Implementing the middle and lower bits with current sources, instead of an R-2R ladder, enhances its dynamic perfor- mance for multitone or low amplitude signals and helps maintain the DAC’s high output impedance (i.e., >100 k W). All of these current sources are switched to one or the other of the two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. The switches are based on the architecture that was pioneered in the AD9764 family, with further refinements to reduce distortion contributed by the switching transient. This switch architecture also reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. The analog and digital sections of the AD9742 have separate power supply inputs (i.e., AVDD and DVDD) that can operate independently over a 3.0 V to 3.6 V range. The digital section, which is capable of operating up to a 165 MSPS clock rate, consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1.2 V band gap voltage reference, and a reference control amplifier. The DAC full-scale output current is regulated by the refer- ence control amplifier and can be set from 2 mA to 20 mA via an external resistor, RSET, connected to the full-scale adjust (FSADJ) pin. The external resistor, in combination with both the reference control amplifier and voltage reference, VREFIO, sets the reference current IREF, which is replicated to the segmented current sources with the proper scaling factor. The full-scale current, IOUTFS, is 32 times IREF. REFERENCE OPERATION The AD9742 contains an internal 1.2 V band gap reference. The internal reference can be disabled by raising REFLO to AVDD. It can also be easily overridden by an external reference with no effect on performance. REFIO serves as either an input or output depending on whether the internal or an external reference is used. To use the internal reference, simply decouple the REFIO pin to ACOM with a 0.1 mF capacitor and connect REFLO to ACOM via a resistance less than 5 W. The internal reference voltage will be present at REFIO. If the voltage at REFIO is to be used anywhere else in the circuit, an external buffer amplifier with an input bias current of less than 100 nA should be used. An example of the use of the internal reference is given in Figure 4. 150pF +1.2V REF AVDD REFLO CURRENT SOURCE ARRAY 3.3V REFIO FS ADJ 2k 0.1 F AD9742 ADDITIONAL LOAD OPTIONAL EXTERNAL REF BUFFER Figure 4. Internal Reference Configuration An external reference can be applied to REFIO as shown in Figure 5. The external reference may provide either a fixed refer- ence voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1 mF compensation capacitor is not required since the internal refer- ence is overridden, and the relatively high input impedance of REFIO minimizes any loading of the external reference. 150pF +1.2V REF AVDD REFLO CURRENT SOURCE ARRAY 3.3V REFIO FS ADJ RSET AD9742 EXTERNAL REF IREF = VREFIO/RSET AVDD REFERENCE CONTROL AMPLIFIER VREFIO Figure 5. External Reference Configuration DIGITAL DATA INPUTS (DB11–DB0) 150pF +1.20V REF AVDD ACOM REFLO PMOS CURRENT SOURCE ARRAY 3.3V SEGMENTED SWITCHES FOR DB11–DB3 LSB SWITCHES REFIO FS ADJ DVDD DCOM CLOCK 3.3V RSET 2k 0.1 F IOUTA IOUTB AD9742 SLEEP LATCHES IREF VREFIO CLOCK IOUTB IOUTA RLOAD 50 VOUTB VOUTA RLOAD 50 VDIFF = VOUTA – VOUTB MODE Figure 3. Simplified Block Diagram |
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