MC34163, MC33163

http://onsemi.com

9

The switch current is converted to a voltage by inserting

monitored by the Current Sense comparator. If the voltage

will set the latch and terminate output switch conduction on

a

cycle−by−cycle

basis.

This

Comparator/Latch

configuration ensures that the Output Switch has only a

single on−time during a given oscillator cycle. The

RSC +

0.25 V

Ipk (Switch)

Figures 12 and 13 show that the Current Sense comparator

threshold is tightly controlled over temperature and has a

typical input bias current of 1.0

mA. The propagation delay

from the comparator input to the Output Switch is typically

circuit layout should be minimized. This will prevent

unwanted voltage spikes that may falsely trip the Current

Limit comparator.

Internal thermal shutdown circuitry is provided to protect

the IC in the event that the maximum junction temperature

is exceeded. When activated, typically at 170

°C, the Latch

is forced into the “Set” state, disabling the Output Switch.

This feature is provided to prevent catastrophic failures from

accidental device overheating. It is not intended to be used

as a replacement for proper heatsinking.

Driver and Output Switch

To aid in system design flexibility and conversion

efficiency, the driver current source and collector, and

output switch collector and emitter are pinned out

separately. This allows the designer the option of driving the

output switch into saturation with a selected force gain or

driving it near saturation when connected as a Darlington.

The output switch has a typical current gain of 70 at 2.5 A

and is designed to switch a maximum of 40 V collector to

emitter, with up to 3.4 A peak collector current. The

RSC(min) +

0.25 V

3.4 A +

0.0735 W

When configured for step−down or voltage−inverting

applications, as in Figures 21 and 25, the inductor will

forward bias the output rectifier when the switch turns off.

Rectifiers with a high forward voltage drop or long turn−on

delay time should not be used. If the emitter is allowed to go

sufficiently negative, collector current will flow, causing

additional device heating and reduced conversion

efficiency.

Figure 10 shows that by clamping the emitter to 0.5 V, the

collector current will be in the range 10

mA over

temperature. A 1N5822 or equivalent Schottky barrier

rectifier is recommended to fulfill these requirements.

A bootstrap input is provided to reduce the output switch

saturation voltage in step−down and voltage−inverting

converter applications. This input is connected through a

series resistor and capacitor to the switch emitter and is used

+7.0 V. The capacitor’s equivalent series resistance must

limit the zener current to less than 100 mA. An additional

series resistor may be required when using tantalum or other

low ESR capacitors. The equation below is used to calculate

a minimum value bootstrap capacitor based on a minimum

zener voltage and an upper limit current source.

CB(min) + I Dt

DV +

4.0 mA ton

4.0 V +

0.001 ton

Parametric operation of the MC34163 is guaranteed over

a supply voltage range of 2.5 V to 40 V. When operating

below 3.0 V, the Bootstrap Input should be connected to

1.7 V at room temperature is possible.

Package

The MC34163 is contained in a heatsinkable 16−lead

plastic dual−in−line package in which the die is mounted on

a special heat tab copper alloy lead frame. This tab consists

of the four center ground pins that are specifically designed

to improve thermal conduction from the die to the circuit

board. Figures 17 and 18 show a simple and effective

method of utilizing the printed circuit board medium as a

heat dissipater by soldering these pins to an adequate area of

copper foil. This permits the use of standard layout and

mounting practices while having the ability to halve the

junction−to−air thermal resistance. These examples are for

a symmetrical layout on a single−sided board with two

ounce per square foot of copper.

APPLICATIONS

The following converter applications show the simplicity

and flexibility of this circuit architecture. Three main

converter topologies are demonstrated with actual test data

shown below each of the circuit diagrams.